MT40A512M8RH-075E Datasheet, PDF (117/365 Pages) Micron Technology – DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
V_REFDQ Calibration
V_REFDQ Calibration
The V_REFDQ level, which is used by the DRAM DQ input receivers, is internally gener-
ated. The DRAM V _REFDQ does not have a default value upon power-up and must be set
to the desired value, usually via V_REFDQ calibration mode. If PDA or PPR modes (hPPR or
sPPR) are used prior to V_REFDQ calibration, V_REFDQ should initially be set at the midpoint
between the V_DD,max, and the LOW as determined by the driver and ODT termination
selected with wide voltage swing on the input levels and setup and hold times of ap-
proximately 0.75UI. The memory controller is responsible for V _REFDQ calibration to de-
termine the best internal V_REFDQ level. The V _REFDQ calibration is enabled/disabled via
MR6[7], MR6[6] selects Range 1 (60% to 92.5% of V_DDQ) or Range 2 (45% to 77.5% of
V_DDQ), and an MRS protocol using MR6[5:0] to adjust the V_REFDQ level up and down.
MR6[6:0] bits can be altered using the MRS command if MR6[7] is disabled. The DRAM
controller will likely use a series of writes and reads in conjunction with V_REFDQ adjust-
ments to obtain the best V_REFDQ, which in turn optimizes the data eye.
The internal V_REFDQ specification parameters are voltage range, step size, V_REF step
time, V_REF full step time, and V_REF valid level. The voltage operating range specifies the
minimum required V_REF setting range for DDR4 SDRAM devices. The minimum range is
defined by V_REFDQ,min and V_REFDQ,max. As noted, a calibration sequence, determined by
the DRAM controller, should be performed to adjust V_REFDQ and optimize the timing
and voltage margin of the DRAM data input receivers. The internal V_REFDQ voltage value
may not be exactly within the voltage range setting coupled with the V_REF set tolerance;
the device must be calibrated to the correct internal V_REFDQ voltage.
Figure 62: V_REFDQ Voltage Range
V_DDQ
V_REF
range
V_REF,max
V_REF,min
V_SWING small
V_SWING large
System variance
Total range
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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