MT40A512M8RH-075E Datasheet, PDF (345/365 Pages) Micron Technology – DDR4 SDRAM

Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)
DDR4-1600
DDR4-1866
DDR4-2133
Parameter
Symbol
Min Max Min Max Min Max
CA Parity Timing
Parity latency
PL
4
–
4
–
4
–
Commands uncertain to be executed dur-
ing this time
t_{PAR_UN-}
KNOWN
–
PL
–
PL
–
PL
Delay from errant command to ALERT_n ^tPAR_ALERT_O –
PL +
–
PL+
–
PL +
assertion
N
6ns
6ns
6ns
Pulse width of ALERT_n signal when as- ^tPAR_ALERT_P 48
96
56
112
64
128
serted
W
Time from alert asserted until DES com- ^tPAR_ALERT_RS –
43
–
50
–
57
mands required in persistent CA parity
P
mode
CAL Timing
CS_n to command address latency
t_CAL
3
–
4
–
4
–
CS_n to command address latency in
gear-down mode
t_CALg
N/A
–
N/A
–
N/A
–
MPSM Timing
Command path disable delay upopn
MPSM entry
t_MPED
MIN = ^tMOD (MIN) + ^tCPDED (MIN)
Valid clock requirement after MPSM
entry
t_CKMPE
MIN = ^tMOD (MIN) + ^tCPDED (MIN)
Valid clock requirement before MPSM
exit
t_CKMPX
MIN = ^tCKSRX (MIN)
Exit MPSM to commands not requiring a
locked DLL
t_XMP
t_{XS (MIN)}
Exit MPSM to commands requiring a
locked DLL
t_XMPDLL
MIN = ^tXMP (MIN) + ^tXSDLL (MIN)
CS setup time to CKE
t_{MPX_S}
MIN = ^tIS (MIN) + ^tIH (MIN)
CS_n HIGH hold time to CKE rising edge
t_{MPX_HH}
MIN = ^tXP
CS_n LOW hold time to CKE rising edge
t_{MPX_LH}
12 ^tXMP-1 12 ^tXMP-1 12 ^tXMP-1
0ns
0ns
0ns
Connectivity Test Timing
TEN pin HIGH to CS_n LOW – Enter CT
mode
t_{CT_Enable}
200
–
200
–
200
–
DDR4-2400
Min Max
5
–
–
PL
–
PL +
6ns
72
144
–
64
5
–
N/A
–
12 ^tXMP-1
0ns
200
–
Unit
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
ns
ns
ns
ns
Notes
20
1
1
1
1