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| MT47H64M16BT-37EA Datasheet, PDF (68/134 Pages) Micron Technology – DDR2 SDRAM | |||
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Figure 29: Nominal Slew Rate for tDH
DQS1
DQS#1
VDDQ
tIS
tIH
VIH(AC)min
1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
tIS
tIH
VIH(DC)min
DC to VREF
region
VREF(DC)
VIL(DC)max
Nominal
slew rate
Nominal
slew rate
DCretogiVonREF
VIL(AC)max
VSS
Hrisoilndgssleigwnaral te=
VREF(DC) - VIL(DC)max
ÎTR
ÎTR
ÎTF
Hold slew rate
falling signal
=
VIH(DC)min - VREF(DC)
ÎTF
Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
Figure 30: Tangent Line for tDH
DQS1
DQS#1
VDDQ
tIS
tIH
tIS
tIH
VIH(AC)min
VIH(DC)min
DC to VREF
region
VREF(DC)
VIL(DC)max
Tangent
line
Nominal
line
Tangent
line
Nominal
line
DC to VREF
region
VIL(AC)max
VSS
ÎTR
ÎTF
Hold slew rate
rising signal
=
Tangent line (VREF[DC] - VIL[DC]max)
ÎTR
Hold slew rate
falling signal
=
Tangent
line
(VIH[DC]min
ÎTF
-
VREF[DC])
Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
PDF: 09005aef821ae8bf
1GbDDR2.pdf â Rev. V 6/10 EN
68
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.
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