MT47H64M16BT-37EA Datasheet, PDF (32/134 Pages) Micron Technology – DDR2 SDRAM

1Gb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – I_DD Parameters
Table 11: DDR2 I_DD Specifications and Conditions (Die Revision H) (Continued)
Notes: 1–7 apply to the entire table
Parameter/Condition
Operating burst read current: All banks
open, continuous burst reads, I_OUT = 0mA; BL =
4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRAS =
t_{RAS MAX (IDD),} t_{RP =} t_{RP (IDD); CKE is HIGH, CS#}
is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switch-
ing
Burst refresh current: ^tCK = ^tCK (I_DD); RE-
FRESH command at every ^tRFC (I_DD) interval;
CKE is HIGH, CS# is HIGH between valid com-
mands; Other control and address bus inputs
are switching; Data bus inputs are switching
Symbol
I_DD4R
I_DD5
Configuration
x4, x8
x16
x4, x8
x16
-187E
150
190
180
210
-25E/
-25
120
150
145
150
Self refresh current: CK and CK# at 0V; CKE ≤
I_DD6
x4, x8, x16
7
7
0.2V; Other control and address bus inputs are
floating; Data bus inputs are floating
I_DD6L
5
5
Operating bank interleave read
I_DD7
current: All bank interleaving reads, I_OUT =
0mA; BL = 4, CL = CL (I_DD), AL = ^tRCD (I_DD) - 1 ×
t_{CK (IDD);} t_{CK =} t_{CK (IDD),} t_{RC =} t_{RC (IDD),} t_{RRD =}
t_{RRD (IDD),} t_{RCD =} t_{RCD (IDD); CKE is HIGH, CS# is}
HIGH between valid commands; Address bus in-
puts are stable during deselects; Data bus inputs
are switching; See on page for details
x4, x8
x16
250
210
300
260
-3E/
-3
Units
110
mA
125
140
mA
145
7
mA
5
185
mA
230
Notes:
1. I_DD specifications are tested after the device is properly initialized. 0°C ≤ T_C ≤ +85°C.
2. V_DD = +1.8V ±0.1V, V_DDQ = +1.8V ±0.1V, V_DDL = +1.8V ±0.1V, V_REF = V_DDQ/2.
3. I_DD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
UDQS#. I_DD values must be met with all combinations of EMR bits 10 and 11.
5. Definitions for I_DD conditions:
LOW
HIGH
Stable
V_IN ≤ V_IL(AC)max
V_IN ≥ V_IH(AC)min
Inputs stable at a HIGH or LOW level
Floating Inputs at V_REF = V_DDQ/2
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
two clocks) for address and control signals
Switching Inputs changing between HIGH and LOW every other data transfer (once
per clock) for DQ signals, not including masks or strobes
6. I_DD1, I_DD4R, and I_DD7 require A12 in EMR to be enabled during testing.
7. The following I_DD values must be derated (I_DD limits increase) on IT-option and AT-op-
tion devices when operated outside of the range 0°C ≤ T_C ≤ 85°C:
When I_DD2P and I_DD3P(SLOW) must be derated by 4%; I_DD4R and I_DD5W must be derat-
T_C ≤ 0°C ed by 2%; and I_DD6 and I_DD7 must be derated by 7%
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
32
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