MT47H64M16BT-37EA Datasheet, PDF (130/134 Pages) Micron Technology – DDR2 SDRAM

1Gb: x4, x8, x16 DDR2 SDRAM
ODT Timing
MRS Command to ODT Update Delay
During normal operation, the value of the effective termination resistance can be
changed with an EMRS set command. ^tMOD (MAX) updates the R_TT setting.
Figure 81: Timing for MRS Command to ODT Update Delay
T0
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Command
EMRS1
NOP
NOP
NOP
NOP
NOP
CK#
CK
ODT2
Internal
R_TT setting
tAOFD
0ns
Old setting
tMOD
Undefined
2
tIS
New setting
Indicates a break in
time scale
Notes:
1. The LM command is directed to the mode register, which updates the information in
EMR (A6, A2), that is, R_TT (nominal).
2. To prevent any impedance glitch on the channel, the following conditions must be met:
t_{AOFD must be met before issuing the LM command; ODT must remain LOW for the}
entire duration of the ^tMOD window until ^tMOD is met.
Figure 82: ODT Timing for Active or Fast-Exit Power-Down Mode
CK#
T0
T1
T2
T3
T4
T5
T6
CK
tCK
tCH tCL
Command
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Address
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CKE
ODT
R_TT
tAOND
tAOFD
tAON _(MIN)
tAON _(MAX)
R_TT Unknown
tAOF _(MAX)
tAOF _(MIN)
R_TT On
Don’t Care
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
130
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