MT47H64M16BT-37EA Datasheet, PDF (111/134 Pages) Micron Technology – DDR2 SDRAM

1Gb: x4, x8, x16 DDR2 SDRAM
WRITE
Figure 63: Bank Write – Without Auto Precharge
CK#
T0
T1
T2
T3
T4
T5 T5n T6 T6n T7
T8
T9
CK
tCK
tCH tCL
CKE
Command
NOP1
ACT
NOP1
WRITE2
NOP1
NOP1
NOP1
NOP1
NOP1
PRE
Address
A10
Bank select
DQS, DQS#
DQ6
DM
RA
RA
Bank x
tRCD
Col n
3
Bank x
WL = 2
WL ±tDQSS (NOM)
tRAS
5
tWPRE
D_nI
tDQSL tDQSH tWPST
tWR
All banks
One bank
Bank x⁴
tRP
Transitioning Data
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 and AL = 0 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T9.
5. Subsequent rising DQS signals must align to the clock within ^tDQSS.
6. DI n = data-in for column n; subsequent elements are applied in the programmed order.
7. ^tDSH is applicable during ^tDQSS (MIN) and is referenced from CK T5 or T6.
8. ^tDSS is applicable during ^tDQSS (MAX) and is referenced from CK T6 or T7.
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
111
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.