MT40A1G4RH-075E Datasheet, PDF (59/365 Pages) Micron Technology – Programmable data strobe preambles

4Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 4
easy repair method of the device after placed in the system. One row per bank can be
repaired. The repair process is revocable by either doing a reset or power-down or by
rewriting a new address in the same bank.
WRITE Preamble
Programmable WRITE preamble, ^tWPRE, can be set to 1^tCK or 2^tCK via the MR4 register.
The 1^tCK setting is similar to DDR3. However, when operating in 2^tCK WRITE preamble
mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL
setting supported in the applicable ^tCK range.
When operating in 2^tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable ^tCK
range. Some even settings will require addition of 2 clocks. If the alternate longer CWL
was used, the additional clocks will not be required.
READ Preamble
Programmable READ preamble ^tRPRE can be set to 1^tCK or 2^tCK via the MR4 register.
Both the 1^tCK and 2^tCK DDR4 preamble settings are different from that defined for the
DDR3 SDRAM. Both DDR4 READ preamble settings may require the memory controller
to train (or read level) its data strobe receivers using the READ preamble training.
READ Preamble Training
Programmable READ preamble training can be set to 1^tCK or 2^tCK. This mode can be
used by the memory controller to train or READ level its data strobe receivers.
Temperature-Controlled Refresh
When temperature-controlled refresh mode is enabled, the device may adjust the inter-
nal refresh period to be longer than ^tREFI of the normal temperature range by skipping
external REFRESH commands with the proper gear ratio. For example, the DRAM tem-
perature sensor detected less than 45°C. Normal temperature mode covers the range of
0°C to 85°C, while the extended temperature range covers 0°C to 95°C.
Command Address Latency
COMMAND ADDRESS LATENCY (CAL) is a power savings feature and can be enabled
or disabled via the MRS setting. CAL is defined as the delay in clock cycles (^tCAL) be-
tween a CS_n registered LOW and its corresponding registered command and address.
The value of CAL (in clocks) must be programmed into the mode register and is based
on the roundup (in clocks) of [^tCK(ns)/^tCAL(ns)].
Internal V_REF Monitor
The device generates its own internal V_REFDQ. This mode may be enabled during V _REFDQ
training, and when enabled, V_{REF,time-short} and V_{REF,time-long} need to be increased by 10ns
if DQ0, DQ1, DQ2, or DQ3 have 0pF loading. An additional 15ns per pF of loading is also
needed.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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