MT40A1G4RH-075E Datasheet, PDF (331/365 Pages) Micron Technology – Programmable data strobe preambles

4Gb: x4, x8, x16 DDR4 SDRAM
Speed Bin Tables
Table 150: DDR4-1866 Speed Bins and Operating Conditions
DDR4-1866 Speed Bin
CL-nRCD-nRP
Parameter
Internal READ command to first data
Internal READ command to first data
with read DBI enabled
ACTIVATE to internal READ or WRITE
delay time
PRECHARGE command period
ACTIVATE-to-PRECHARGE command
period
ACTIVATE-to-ACTIVATE or REFRESH
command period
READ:
nonDBI READ: DBI WRITE
CL = 9 CL = 11
CWL = 9
CL = 10 CL = 12
CWL = 9
CL = 10 CL = 12
CWL = 11
CL = 11 CL = 13
CWL = 9, 11
CL = 12 CL = 14
CWL = 9, 11
CL = 12 CL = 14
CWL = 10, 12
CL = 13 CL = 15
CWL = 10, 12
CL = 14 CL = 16
CWL = 10, 12
Supported CL settings
Supported CL settings with read DBI
Supported CWL settings
Symbol
t_AA
t_{AA_DBI}
t_RCD
t_RP
t_RAS
t_RC8
Symbol
t_CK6
t_CK6
t_CK6
t_CK6
t_CK6
t_CK6
t_CK6
t_CK6
-107F
12-12-12
Min
Max
12.85
19.00
t_AA
(MIN) +
2nCK
t_AA
(MAX) +
2nCK
12.85
–
12.85
34
–
9 × ^tREFI
t_{RAS +}
–
t_RP
Min
Max
1.5
1.9
1.5
1.9
Reserved
Reserved
1.25
<1.5
1.071 <1.25
1.071 <1.25
1.071 <1.25
9, 10, 12–14
11,12,14-16
9–12
-107E
13-13-13
Min
Max
13.92⁷ 19.00
t_AA
(MIN) +
2nCK
t_AA
(MAX) +
2nCK
13.92 ⁷
–
13.92 ⁷
–
34
9 × ^tREFI
t_{RAS +}
–
t_RP
Min
Max
1.5
1.9
1.5
1.9
Reserved
1.25
<1.5
1.25
<1.5
Reserved
1.071 <1.25
1.071 <1.25
9, 11–14
11, 13–16
9–12
-107
14-14-14
Min
Max
15.00
19.00
t_AA
(MIN) +
2nCK
t_AA
(MAX) +
2nCK
15.00
–
Unit
ns
ns
ns
15.00
–
ns
34
9 × ^tREFI ns
t_{RAS +}
–
ns
t_RP
Min
Max
Reserved
1.5
1.9
Reserved
Reserved
1.25
<1.5
Reserved
Reserved
1.071 <1.25
10, 12, 14
12, 14, 16
9–12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
nCK
nCK
nCK
Notes:
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
2. When operating in 2^tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable ^tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. 12.85ns is the minimum value of ^tAA and ^tRP when operating at DDR4-1866 at ^tCK
(AVG) MIN = 1.071ns and is only a reference that does not consider the down binning
strategy that 12.5ns supports.
5. 13.92ns is the minimum value of ^tAA and ^tRP when operating at DDR4-1866 at ^tCK
(AVG) MIN = 1.071ns and is only a reference that does not consider the down binning
strategy that 13.75ns supports.
6. ^tCK (AVG) MIN.
7. The DRAM supports 13.5ns with CL9 operation and 13.75ns with CL11 operation at de-
fined clock rates.
8. When calculating ^tRC and ^tRP in clocks, values may not be used in a combination that
would violate ^tRAS.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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