MT40A1G4RH-075E Datasheet, PDF (254/365 Pages) Micron Technology – Programmable data strobe preambles

4Gb: x4, x8, x16 DDR4 SDRAM
Synchronous ODT Mode
Figure 200: Synchronous ODT Timing with BL8
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diff_CK
Command
ODT
DRAM_R_TT
DODTLon = WL - 2
R_TT(Park)
t_{ADC (MAX)}
t_{ADC (MIN)}
DODTLoff = WL - 2
R_TT(NOM)
t_{ADC (MAX)}
t_{ADC (MIN)}
R_TT(Park)
Transitioning
Notes: 1. Example for CWL = 9, AL = 0, PL = 0; DODTLon = AL + PL + CWL - 2 = 7; DODTLoff = AL +
PL + CWL - 2 = 7.
2. ODT must be held HIGH for at least ODTH8 after assertion (T1).
Figure 201: Synchronous ODT with BC4
T0
T1
T2
T3
T4
T5
T18
T19
T20 T21
T22
T23
T36
T37
T38
T39
T40
T41
42
diff_CK
Command
ODTH4
WRS4
ODT
DRAM_R_TT
DODTLon = CWL - 2
R_TT(Park)
t_{ADC (MAX)}
t_{ADC (MIN)}
DODTLoff = WL - 2
ODTLcnw= WL - 2
ODTLcwn4 = ODTLcnw + 4
t_{ADC (MAX)}
t_{ADC (MIN)}
R_TT(NOM)
R_TT(Park)
t_{ADC (MAX)}
t_{ADC (MIN)}
R_TT(WR)
t_{ADC (MAX)}
t_{ADC (MIN)}
R_TT(Park)
Transitioning
Notes: 1. Example for CWL = 9, AL = 10, PL = 0; DODTLon/off = AL + PL+ CWL - 2 = 17; ODTcnw =
AL + PL+ CWL - 2 = 17.
2. ODT must be held HIGH for at least ODTH4 after assertion (T1).
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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