MT40A1G4RH-075E Datasheet, PDF (333/365 Pages) Micron Technology – Programmable data strobe preambles

4Gb: x4, x8, x16 DDR4 SDRAM
Speed Bin Tables
Table 152: DDR4-2400 Speed Bins and Operating Conditions
DDR4-2400 Speed Bin
CL-nRCD-nRP
Parameter
Internal READ command to first data
Internal READ command to first data
with read DBI enabled
ACTIVATE to internal READ or WRITE
delay time
PRECHARGE command period
ACTIVATE-to-PRECHARGE command
period
ACTIVATE-to-ACTIVATE or REFRESH
command period
READ: READ: DBI WRITE
nonDBI
CL = 9 CL = 11
CWL = 9
CL = 10 CL = 12
CWL = 9
CL = 10 CL = 12
CWL = 9, 11
CL = 11 CL = 13
CWL = 9, 11
CL = 12 CL = 14
CWL = 9, 11
CL = 12 CL = 14
CWL = 10, 12
CL = 13 CL = 15
CWL = 10, 12
CL = 14 CL = 16
CWL = 10, 12
CL = 14 CL =17
CWL = 11, 14
CL = 15 CL = 18
CWL = 11, 14
CL = 16 CL = 19
CWL = 11, 14
CL = 15 CL = 18
CWL = 12, 16
CL = 16 CL = 19
CWL = 12, 16
CL = 17 CL = 20
CWL = 12, 16
CL = 18 CL = 21
CWL = 12, 16
Supported CL settings
Supported CL settings with read DBI
Supported CWL settings
Symbol
t_AA
t_{AA_DBI}
t_RCD
t_RP
t_RAS
t_RC6
Symbol
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
-083F
15-15-15
Min
Max
12.5
19.00
t_AA
(MIN) +
3nCK
t_AA
(MAX) +
3nCK
12.5
–
12.5
32
–
9 × ^tREFI
t_{RAS +}
t_RP
Min
–
Max
1.5
1.9
1.5
1.9
Reserved
Reserved
1.25
<1.5
Reserved
Reserved
1.071 <1.25
Reserved
Reserved
0.937 <1.071
0.833 <0.937
0.833 <0.937
0.833 <0.937
0.833 <0.937
9, 10, 12, 14–18
11, 12, 14, 16, 18-21
9, 10, 11, 12, 14, 16
-083E
16-16-16
Min
Max
13.32
19.00
t_AA
(MIN) +
3nCK
t_AA
(MAX) +
3nCK
13.32
–
13.32
32
–
9 × ^tREFI
t_{RAS +}
t_RP
Min
–
Max
1.5
1.9
1.5
1.9
Reserved
1.25
<1.5
1.25
<1.5
Reserved
1.071 <1.25
1.071 <1.25
Reserved
0.937⁵ <1.071
0.937 <1.071
Reserved
0.833 <0.937
0.833 <0.937
0.833 <0.937
9–18
11, 13–16, 18–21
9, 10, 11, 12, 14, 16
-083
17-17-17
Min
Max
14.16
19.00
t_AA
(MIN) +
3nCK
t_AA
(MAX) +
3nCK
14.16
–
14.16
32
–
9 × ^tREFI
t_{RAS +}
t_RP
Min
–
Max
Reserved
1.5
1.9
Reserved
1.25
<1.5
1.25
<1.5
Reserved
1.071 <1.25
1.071 <1.25
Reserved
0.937 <1.071
0.937 <1.071
Reserved
Reserved
0.833 <0.937
0.833 <0.937
10–18
12–16, 18–21
9, 10, 11, 12, 14, 16
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nCK
nCK
nCK
Notes:
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
2. When operating in 2^tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable ^tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. ^tCK (AVG) MIN.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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