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MT40A1G4RH-075E Datasheet, PDF (37/365 Pages) Micron Technology – Programmable data strobe preambles
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4Gb: x4, x8, x16 DDR4 SDRAM
RESET and Initialization Procedure
15. The device will be ready for normal operation. Once the DRAM has been initial-
ized, if the DRAM is in an idle state longer than 960ms, then either (a) REF com-
mands must be issued within tREFI constraints (specification for posting allowed)
or (b) CKE or CS_n must toggle once within every 960ms interval of idle time. For
debug purposes, the 960ms delay limit maybe extended to 60 minutes provided
the DRAM is operated in this debug mode for no more than 360 cumulative hours.
A stable valid VDD level is a set DC level (0Hz to 250 KHz) and must be no less than
VDD,min and no greater than VDD,max. If the set DC level is altered anytime after initializa-
tion, the DLL reset and calibrations must be performed again after the new set DC level
is stable. AC noise of ±60mV (greater than 250 KHz) is allowed on VDD provided the
noise doesn't alter VDD to less than VDD,min or greater than VDD,max.
A stable valid VDDQ level is a set DC level (0Hz to 250 KHz) and must be no less than
VDDQ,min and no greater than VDDQ,max. If the set DC level is altered anytime after initial-
ization, the DLL reset and calibrations must be performed again after the new set DC
level is stable. AC noise of ±60mV (greater than 250 KHz) is allowed on VDDQ provided
the noise doesn't alter VDDQ to less than VDDQ,min or greater than VDDQ,max.
A stable valid VPP level is a set DC level (0Hz to 250 KHz) and must be no less than
VPP,min and no greater than VPP,max. If the set DC level is altered anytime after initializa-
tion, the DLL reset and calibrations must be performed again after the new set DC level
is stable. AC noise of ±120mV (greater than 250KHz) is allowed on VPP provided the
noise doesn't alter VPP to less than VPP,min or greater than VPP,max.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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