MT40A1G4RH-075E Datasheet, PDF (40/365 Pages) Micron Technology – Programmable data strobe preambles

4Gb: x4, x8, x16 DDR4 SDRAM
Programming Mode Registers
• Condition D: The time V_PP may be less than 2.0V and above V_SS while turning off is
≤15ms per occurrence with a total accumulated time in this state ≤150ms.
Programming Mode Registers
For application flexibility, various functions, features, and modes are programmable in
seven mode registers (MRn) provided by the device as user defined variables that must
be programmed via a MODE REGISTER SET (MRS) command. Because the default val-
ues of the mode registers are not defined, contents of mode registers must be fully ini-
tialized and/or re-initialized; that is, they must be written after power-up and/or reset
for proper operation. The contents of the mode registers can be altered by re-executing
the MRS command during normal operation. When programming the mode registers,
even if the user chooses to modify only a sub-set of the MRS fields, all address fields
within the accessed mode register must be redefined when the MRS command is is-
sued. MRS and DLL RESET commands do not affect array contents, which means these
commands can be executed any time after power-up without affecting the array con-
tents.
The MRS command cycle time, ^tMRD, is required to complete the WRITE operation to
the mode register and is the minimum time required between the two MRS commands
shown in the ^tMRD Timing figure.
Some of the mode register settings affect address/command/control input functionali-
ty. In these cases, the next MRS command can be allowed when the function being up-
dated by the current MRS command is completed. These MRS commands don’t apply
t_{MRD timing to the next MRS command; however, the input cases have unique MR set-}
ting procedures, so refer to individual function descriptions:
• Gear-down mode
• Per-DRAM addressability
• Maximum power saving mode
• CS to command/address latency
• CA parity latency mode
• V_REFDQ training value
• V_REFDQ training mode
• V_REFDQ training range
Some mode register settings may not be supported because they are not required by
certain speed bins.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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