MT29F8G08ADADAH4D Datasheet, PDF (59/132 Pages) Micron Technology – 4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory Features

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4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Column Address Operations
RANDOM DATA INPUT (85h)
The RANDOM DATA INPUT (85h) command changes the column address of the selec-
ted cache register and enables data input on the last-selected die (LUN). This command
is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also ac-
cepted by the selected die (LUN) during cache program operations
(RDY = 1; ARDY = 0).
Writing 85h to the command register, followed by two column address cycles containing
the column address, puts the selected die (LUN) into data input mode. After the second
address cycle is issued, the host must wait at least ^tADL before inputting data. The se-
lected die (LUN) stays in data input mode until another valid command is issued.
Though data input mode is enabled, data input from the host is optional. Data input
begins at the column address specified.
The RANDOM DATA INPUT (85h) command is allowed after the required address cycles
are specified, but prior to the final command cycle (10h, 11h, 15h) of the following com-
mands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE
CACHE (80h-15h), PROGRAM FOR INTERNAL DATA MOVE (85h-10h), and PROGRAM
FOR TWO-PLANE INTERNAL DATA MOVE (85h-11h).
In devices that have more than one die (LUN) per target, the RANDOM DATA INPUT
(85h) command can be used with other commands that support interleaved die (multi-
LUN) operations.
Figure 36: RANDOM DATA INPUT (85h) Operation
As defined for PAGE
(CACHE) PROGRAM
Cycle type
I/O[7:0]
D_IN
D_IN
Command Address Address
t_ADL
Dn Dn + 1
85h
C1
C2
As defined for PAGE
(CACHE) PROGRAM
D_IN
D_IN
D_IN
Dk Dk + 1 Dk + 2
RDY
PDF: 09005aef83b25735
m60a_4gb_8gb_16gb_ecc_nand.pdf - Rev. N 10/12 EN
59
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