MT29F8G08ADADAH4D Datasheet, PDF (54/132 Pages) Micron Technology – 4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory Features

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4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Status Operations
Status Operations
Each die (LUN) provides its status independently of other die (LUNs) on the same target
through its 8-bit status register.
After the READ STATUS (70h) or READ STATUS ENHANCED (78h) command is issued,
status register output is enabled. The contents of the status register are returned on I/
O[7:0] for each data output request.
When the asynchronous interface is active and status register output is enabled,
changes in the status register are seen on I/O[7:0] as long as CE# and RE# are LOW; it is
not necessary to toggle RE# to see the status register update.
While monitoring the status register to determine when a data transfer from the Flash
array to the data register (^tR) is complete, the host must issue the READ MODE (00h)
command to disable the status register and enable data output (see Read Operations).
The READ STATUS (70h) command returns the status of the most recently selected die
(LUN). To prevent data contention during or following an interleaved die (multi-LUN)
operation, the host must enable only one die (LUN) for status output by using the READ
STATUS ENHANCED (78h) command (see Interleaved Die (Multi-LUN) Operations).
With internal ECC enabled, a READ STATUS command is required after completion of
the data transfer (^tR_ECC) to determine whether an uncorrectable read error occurred.
Table 18: Status Register Definition
SR
Program Program Page
Page Read
Bit
Page
Cache Mode Page Read Cache Mode Block Erase
Description
7 Write protect Write protect Write protect Write protect Write protect 0 = Protected
1 = Not protected
6
RDY
RDY¹ cache
RDY
RDY¹ cache
RDY
0 = Busy
1 = Ready
5
ARDY
ARDY²
ARDY
ARDY²
ARDY Don't Care
4
–
–
–
–
–
Don't Care
3
–
–
Rewrite
–
recommended³
–
0 = Normal or uncorrectable
1 = Rewrite recommended
2
–
–
–
–
–
Don't Care
1
FAILC (N - 1) FAILC (N - 1)
Reserved
–
–
Don't Care
0
FAIL
FAIL (N)
FAIL⁴
–
FAIL
0 = Successful PROGRAM/
ERASE/READ
1 = Error in PROGRAM/
ERASE/READ
Notes:
1. Status register bit 6 is 1 when the cache is ready to accept new data. R/B# follows bit 6.
2. Status register bit 5 is 0 during the actual programming operation. If cache mode is
used, this bit will be 1 when all internal operations are complete.
3. A status register bit defined as Rewrite Recommended signifies that the page includes
acertain number of READ errors per sector (512B (main) + 4B (spare) + 8B (parity). A re-
writeof this page is recommended. (Up to a 4-bit error has been corrected if internal
ECC was enabled.)
4. A status register bit defined as FAIL signifies that an uncorrectable READ error has oc-
curred.
PDF: 09005aef83b25735
m60a_4gb_8gb_16gb_ecc_nand.pdf - Rev. N 10/12 EN
54
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