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MT40A1G8WE-083EAAT Datasheet, PDF (274/358 Pages) Micron Technology – Automotive DDR4 SDRAM
8Gb: x8, x16 Automotive DDR4 SDRAM
Electrical Characteristics – AC and DC Differential Input Meas-
urement Levels
measure setup time. For single-ended components of differential signals the require-
ment to reach VSEL,max/VSEH,min has no bearing on timing, but adds a restriction on the
common mode characteristics of these signals.
Figure 215: Single-Ended Requirements for CK
VDD or VDDQ
VSEH,min
VDD/2 or VDDQ/2
VSEL,max
VSS or VSSQ
VSEH
CK
VSEL
Table 100: Single-Ended Requirements for CK
Parameter
Single-ended high level for CK_t,
CK_c
Single-ended low level for CK_t, CK_c
Symbol
VSEH
VSEL
DDR4-1600 / 1866 /
2133 / 2400
Min
Max
VDD/2 +
0.100
Note 3
Note 3
VDD/2 -
0.100
DDR4-2666 / 2933 /
3200
Min
Max
VDD/2 +
0.90
Note 3
Note 3 VDD/2 - 0.90
Unit
V
V
Notes
1, 2
1, 2
Notes:
1. For CK_t, CK_c use VIH(AC) and VIL(AC) of ADD/CMD and VREFCA.
2. ADDR/CMD VIH(AC) and VIL(AC) based on VREFCA.
3. These values are not defined; however, the differential signal (CK_t, CK_c) need to be
within the respective limits, VIH(DC)max and VIL(DC)min for single-ended signals as well as
the limitations for overshoot and undershoot.
Slew Rate Definitions for CK Differential Input Signals
Table 101: CK Differential Input Slew Rate Definition
Description
Differential input slew rate for rising edge
Measured
From
To
VIL,diff,max
VIH,diff,min
Defined by
|VIH,diff,min - VIL,diff,maxΔTRdiff
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
274
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