MT40A1G8WE-083EAAT Datasheet, PDF (207/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
Figure 150: READ with Auto Precharge, Additive Latency, and 1^tCK Preamble
T0
T1
T2
T3
T10
T11
T12
T13
T16
T19
T20
T21
T22
T23
T24
T25
T26
T27
CK_c
CK_t
Command DES
RDA
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
ACT
Bank Group
Address
Address
BGa
Bank a
Col n
BC4 Opertaion
DQS_t,
DQS_c
DQ
BL8 Opertaion
DQS_t,
DQS_c
DQ
AL = CL - 2 = 9
t_RTP
CL = 11
t_RP
DO DO DO DO
n n+1 n+2 n+3
DO DO DO DO DO DO DO DO
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
BGa
Bank a
Row b
Time Break
Transitioning Data
Don’t Care
Notes:
1. RL = 20 (CL = 11, AL = CL - 2), Preamble = 1^tCK, ^tRTP = 6, ^tRP = 11.
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. ^tRTP = 6 setting activated by MR0[11:9] = 001.
5. The example assumes that ^tRC (MIN) is satisfied at the next ACTIVATE command time
(T27).
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
READ Operation with Read Data Bus Inversion (DBI)
Figure 151: Consecutive READ (BL8) with 1^tCK Preamble and DBI in Different Bank Group
T0
CK_c
CK_t
T1
T2
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
Command READ
Bank Group _BGa
Address
Address
Bank
Col n
DQS_t,
DQS_c
DQ
DBI_n
DES
DES
DES
t_{CCD_S = 4}
READ
BGb
Bank
Col b
RL = 11 + 2 (Read DBI adder)
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_RPRE
t_RPST
RL = 11 + 2 (Read DBI adder)
DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO
n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 b b + 1 b + 2 b + 3 b +4 _ b + 5 b + 6 b + 7
DBI DBI DBI DBI DBI DBI DBI DBI DBI DBI DBI DBI DBI DBI DBI DBI
n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 b+4 b+5 b+6 b+7
Time Break
Transitioning Data
Notes: 1. BL = 8, AL = 0, CL = 11, Preamble = 1^tCK, RL = 11 + 2 (Read DBI adder).
Don’t Care
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
207
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