MT40A1G8WE-083EAAT Datasheet, PDF (148/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
SELF REFRESH Operation
Figure 86: Self Refresh Exit with NOP Command
CK_c
CK_t
Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb3 Tc0
t_CKSRX
Tc1 Tc2
Tc3 Tc4
Td0 Td1 Td2 Td3 Te0 Te1
CKE
ODT
CS_n
Command
ADDR
t_{MPX_S}
t_{MPX_LH}
Valid
Note 1, 2
Note 3
SRX NOP NOP NOP NOP DES DES DES DES DES Valid DES Valid
Valid Valid Valid Valid Valid
t_XS
t_{XS +} t_XSDLL
Valid
Valid
Don’t Care
Notes:
1. CS_n = LOW, ACT_n = HIGH, RAS_n/A16 = HIGH, CAS_n/A15 = HIGH, WE_n/A14 = HIGH
at Tb2 (NO OPERATION command).
2. SRX at Tb2 is only allowed when DRAM shared command/address bus is under exiting
max power saving mode.
3. Valid commands not requiring a locked DLL.
4. Valid commands requiring locked DLL.
5. ^tXS_FAST and ^tXS_ABORT are not allowed this case.
6. Duration of CS_n LOW around CKE rising edge must satisfy ^tMPX_S and ^tMPX_LH as de-
fined max power saving mode AC parameters.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
148
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