MT41J256M8 Datasheet, PDF (208/211 Pages) Micron Technology – MT41J512M4 – 64 Meg x 4 x 8 Banks

Figure 118: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit
T0
T1
T2
Ta0
CK#
CK
CKE
COMMAND
t_ANPD
ODT A
asynchronous
DRAM R_TT A
asynchronous
ODT B
asynchronous
or synchronous
R_TT B
asynchronous
or synchronous
ODT C
synchronous
DRAM R_TT C
synchronous
R_TT,nom
t_{AOFPD (MIN)}
t_{AOFPD (MAX)}
R_TT,nom
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t_XPDLL
PDX transition period
ODTLoff + ^tAOF (MIN)
t_{AOFPD (MAX)}
t_{AOFPD (MIN)}
ODTLoff + ^tAOF (MAX)
R_TT,nom
ODTLoff
Td0
Td1
NOP
NOP
t_{AOF (MAX)}
t_{AOF (MIN)}
Note: 1. CL = 6; AL = CL - 1; CWL = 5; ODTLoff = WL - 2 = 8.
Indicates break
in time scale
Transitioning
Don’t Care