MT41J256M8 Datasheet, PDF (130/211 Pages) Micron Technology – MT41J512M4 – 64 Meg x 4 x 8 Banks

2Gb: x4, x8, x16 DDR3 SDRAM
Write Leveling
Write Leveling Mode Exit Procedure
After the DRAM are leveled, they must exit from write leveling mode before the normal
mode can be used. Figure 47 depicts a general procedure for exiting write leveling
mode. After the last rising DQS (capturing a 1 at T0), the memory controller should stop
driving the DQS signals after ^tWLO (MAX) delay plus enough delay to enable the memo-
ry controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls become
undefined when DQS no longer remains LOW, and they remain undefined until ^tMOD
after the MRS command (at Te1).
The ODT input should be de-asserted LOW such that ODTLoff (MIN) expires after the
DQS is no longer driving LOW. When ODT LOW satisfies ^tIS, ODT must be kept LOW (at
~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal
mode can be used. After DQS termination is switched off, write level mode should be
disabled via the MRS command (at Tc2). After ^tMOD is satisfied (at Te1), any valid com-
mand may be registered by the DRAM. Some MRS commands may be issued after ^tMRD
(at Td1).
Figure 47: Write Leveling Exit Procedure
T0
CK#
CK
Command NOP
Address
ODT
R_TT DQS, R_TT DQS#
DQS, DQS#
R_TT(DQ)
DQ
T1
T2
Ta0
Tb0
Tc0
Tc1
NOP
NOP
NOP
NOP
NOP
NOP
R_TT,nom
t_{WLO +} t_WLOE
t_IS
ODTLoff ^{tAOF (MIN)}
t_{AOF (MAX)}
CK = 1
Tc2
Td0
Td1
Te0
Te1
MRS
NOP
Valid
NOP
Valid
t_MRD
MR1
Valid
Valid
t_MOD
Indicates break
in time scale
Undefined Driving Mode
Transitioning
Don’t Care
Note: 1. The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing
CK HIGH just after the T0 state.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
130
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