MT41J256M8 Datasheet, PDF (118/211 Pages) Micron Technology – MT41J512M4 – 64 Meg x 4 x 8 Banks

PRECHARGE
REFRESH
2Gb: x4, x8, x16 DDR3 SDRAM
Commands
The PRECHARGE command is used to de-activate the open row in a particular bank or
in all banks. The bank(s) are available for a subsequent row access a specified time (^tRP)
after the PRECHARGE command is issued, except in the case of concurrent auto pre-
charge. A READ or WRITE command to a different bank is allowed during a concurrent
auto precharge as long as it does not interrupt the data transfer in the current bank and
does not violate any other timing parameters. Input A10 determines whether one or all
banks are precharged. In the case where only one bank is precharged, inputs BA[2:0] se-
lect the bank; otherwise, BA[2:0] are treated as “Don’t Care.”
After a bank is precharged, it is in the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank. A PRECHARGE command is treated as
a NOP if there is no open row in that bank (idle state) or if the previously open row is
already in the process of precharging. However, the precharge period is determined by
the last PRECHARGE command issued to the bank.
The REFRESH command is used during normal operation of the DRAM and is analo-
gous to CAS#-before-RAS# (CBR) refresh or auto refresh. This command is nonpersis-
tent, so it must be issued each time a refresh is required. The addressing is generated by
the internal refresh controller. This makes the address bits a “Don’t Care” during a RE-
FRESH command. The DRAM requires REFRESH cycles at an average interval of 7.8μs
(maximum when T_C ≤ 85°C or 3.9μs maximum when T_C ≤ 95°C). The REFRESH period
begins when the REFRESH command is registered and ends ^tRFC (MIN) later.
To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided. A maximum of eight REFRESH com-
mands can be posted to any given DRAM, meaning that the maximum absolute interval
between any REFRESH command and the next REFRESH command is nine times the
maximum average interval refresh rate. Self refresh may be entered with up to eight RE-
FRESH commands being posted. After exiting self refresh (when entered with posted
REFRESH commands), additional posting of REFRESH commands is allowed to the ex-
tent that the maximum number of cumulative posted REFRESH commands (both pre-
and post-self refresh) does not exceed eight REFRESH commands.
At any given time, a maximum of 16 REFRESH commands can be issued within
2 x ^tREFI.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
118
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