MT41J256M8 Datasheet, PDF (198/211 Pages) Micron Technology – MT41J512M4 – 64 Meg x 4 x 8 Banks

2Gb: x4, x8, x16 DDR3 SDRAM
Synchronous ODT Mode
Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked and
when either R_TT,nom or R_TT(WR) is enabled. Based on the power-down definition, these
modes are:
• Any bank active with CKE HIGH
• Refresh mode with CKE HIGH
• Idle mode with CKE HIGH
• Active power-down mode (regardless of MR0[12])
• Precharge power-down mode if DLL is enabled by MR0[12] during precharge power-
down
ODT Latency and Posted ODT
In synchronous ODT mode, R_TT turns on ODTLon clock cycles after ODT is sampled
HIGH by a rising clock edge and turns off ODTLoff clock cycles after ODT is registered
LOW by a rising clock edge. The actual on/off times varies by ^tAON and ^tAOF around
each clock edge (see Table 90 (page 199)). The ODT latency is tied to the WRITE latency
(WL) by ODTLon = WL - 2 and ODTLoff = WL - 2.
Since write latency is made up of CAS WRITE latency (CWL) and additive latency (AL),
the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT signal.
The device’s internal ODT signal is delayed a number of clock cycles defined by the AL
relative to the external ODT signal. Thus, ODTLon = CWL + AL - 2 and ODTLoff = CWL +
AL - 2.
Timing Parameters
Synchronous ODT mode uses the following timing parameters: ODTLon, ODTLoff,
ODTH4, ODTH8, ^tAON, and ^tAOF. The minimum R_TT turn-on time (^tAON [MIN]) is the
point at which the device leaves High-Z and ODT resistance begins to turn on. Maxi-
mum R_TT turn-on time (^tAON [MAX]) is the point at which ODT resistance is fully on.
Both are measured relative to ODTLon. The minimum R_TT turn-off time (^tAOF [MIN]) is
the point at which the device starts to turn off ODT resistance. The maximum R_TT turn
off time (^tAOF [MAX]) is the point at which ODT has reached High-Z. Both are measured
from ODTLoff.
When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE com-
mand is registered by the DRAM with ODT HIGH, then ODT must remain HIGH until
ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 114 (page 200)).
ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW
or from the registration of a WRITE command until ODT is registered LOW.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
198
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