MT16LSDF6464HY-133D2 Datasheet, PDF (11/22 Pages) Micron Technology – SMALL-OUTLINE SDRAM MODULE

Commands
The Truth Table provides a quick reference of avail-
able commands. This is followed by written descrip-
tion of each command. For a more detailed
256MB, 512MB (x64, DR)
144-PIN SDRAM SODIMM
description of commands and operations, refer to the
128Mb or 256Mb SDRAM component data sheet.
Table 9: Truth Table – SDRAM Commands and DQMB Operation
CKE is HIGH for all commands shown except SELF REFRESH
NAME (FUNCTION)
CS# RAS# CAS# WE# DQMB ADDR DQ
COMMAND INHIBIT (NOP)
HX
X
X
X
X
X
NO OPERATION (NOP)
L
H
H
H
X
X
X
ACTIVE (select bank and activate row)
L
L
H
H
X Bank/Row X
READ (select bank and column, and start READ burst) L H
L
H _L/H⁸ Bank/Col X
WRITE (select bank and column, and start WRITE burst) L H
L
L
L/H^{8 Bank/Col Valid}
BURST TERMINATE
LH
H
L
X
X
Active
PRECHARGE (deactivate row in bank or banks)
L
L
H
L
X
Code
X
AUTO REFRESH or SELF REFRESH
(enter self refresh mode)
L
L
L
H
X
X
X
LOAD MODE REGISTER
L
L
L
L
X Op-code X
Write enable/output enable
–
–
–
–
L
–
Active
Write inhibit/output High-Z
–
–
–
–
H
–
High-Z
NOTES
1
2
2
3
4, 5
6
7
7
NOTE:
1. A0–A11 (256MB) or A0–A12 (512MB) provide device row address, and BA0, BA1 determine which device bank is made
active.
2. A0–A9 (256MB and 512MB) provide device column address; A10 HIGH enables the auto precharge feature (nonpersis-
tent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or
written to.
3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and
BA0, BA1 are “Don’t Care.”
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
6. A0–A11 define the op-code written to the mode register; for the 256MB and 512MB, A12 should be driven low.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
11
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©2006 Micron Technology, Inc. All rights reserved.