PIC16F877-20L Datasheet, PDF (73/218 Pages) Microchip Technology – 28/40-Pin 8-Bit CMOS FLASH Microcontrollers

9.2 MSSP I²C Operation
The MSSP module in I²C mode, fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits in
hardware, to determine a free bus (multi-master func-
tion). The MSSP module implements the standard mode
specifications, as well as 7-bit and 10-bit addressing.
Refer to Application Note AN578, "Use of the SSP
Module in the I ²C Multi-Master Environment."
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independent of device frequency.
FIGURE 9-5:
I²C SLAVE MODE BLOCK
DIAGRAM
Read
Internal
Data Bus
Write
SCL
SDA
SSPBUF Reg
Shift
Clock
SSPSR Reg
MSb
LSb
Match Detect
Addr Match
SSPADD Reg
START and
STOP bit Detect
Set, Reset
S, P bits
(SSPSTAT Reg)
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins are automatically config-
ured when the I²C mode is enabled. The SSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON<5>).
The MSSP module has six registers for I²C operation.
They are the:
• SSP Control Register (SSPCON)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly
accessible
• SSP Address Register (SSPADD)
PIC16F87X
The SSPCON register allows control of the I²C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I²C modes to be selected:
• I²C Slave mode (7-bit address)
• I²C Slave mode (10-bit address)
• I²C Master mode, clock = OSC/4 (SSPADD +1)
• I²C firmware modes (provided for compatibility to
other mid-range products)
Before selecting any I²C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropri-
ate TRIS bits. Selecting an I²C mode by setting the
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I²C mode. Pull-up resis-
tors must be provided externally to the SCL and SDA
pins for the proper operation of the I²C module.
The CKE bit (SSPSTAT<6:7>) sets the levels of the
SDA and SCL pins in either Master or Slave mode.
When CKE = 1, the levels will conform to the SMBus
specification. When CKE = 0, the levels will conform to
the I²C specification.
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit, specifies if the received
byte was data or address, if the next byte is the com-
pletion of 10-bit address, and if this will be a read or
write data transfer.
SSPBUF is the register to which the transfer data is
written to, or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.
The SSPADD register holds the slave address. In
10-bit mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
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DS30292D-page 73