PIC16F877-20L Datasheet, PDF (130/218 Pages) Microchip Technology – 28/40-Pin 8-Bit CMOS FLASH Microcontrollers

PIC16F87X
12.10.1 INT INTERRUPT
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit, GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 12.13 for details on SLEEP
mode.
12.10.2 TMR0 INTERRUPT
An overflow (FFh  00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (Section 5.0).
12.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>)
(Section 3.2).
12.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt, (i.e., W register and STATUS
register). This will have to be implemented in software.
For the PIC16F873/874 devices, the register W_TEMP
must be defined in both banks 0 and 1 and must be
defined at the same offset from the bank base address
(i.e., If W_TEMP is defined at 0x20 in bank 0, it must
also be defined at 0xA0 in bank 1). The registers,
PCLATH_TEMP and STATUS_TEMP, are only defined
in bank 0.
Since the upper 16 bytes of each bank are common in
the PIC16F876/877 devices, temporary holding regis-
ters W_TEMP, STATUS_TEMP, and PCLATH_TEMP
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for con-
text save and restore. The same code shown in
Example 12-1 can be used.
EXAMPLE 12-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
MOVWF
SWAPF
SWAPF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;(Insert user code here)
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
DS30292D-page 130
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