PIC18F4580 Datasheet, PDF (445/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
FIGURE 27-14: EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
70
71
72
80
MSb
83
78
79
79
78
bit 6 - - - - - -1
LSb
SDI
Note:
MSb In
74
73
75, 76
bit 6 - - - -1
Refer to Figure 27-4 for load conditions.
77
LSb In
TABLE 27-16: EXAMPLE SPI™ MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
TCY
—
71
TSCH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TSCL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
—
73A TB2B
Last Clock Edge of Byte1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
—
75
TDOR
SDO Data Output Rise Time
PIC18FXXXX
—
25
PIC18LFXXXX
45
76
TDOF
SDO Data Output Fall Time
—
25
77
TSSH2DOZ SS ↑ to SDO Output High-Impedance
10
50
78
TSCR
SCK Output Rise Time (Master mode) PIC18FXXXX
—
25
PIC18LFXXXX
45
79
TSCF
SCK Output Fall Time (Master mode)
—
25
80
TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXXXX
—
50
TSCL2DOV
PIC18LFXXXX
100
83
TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns VDD = 2.0V
ns
ns
ns
ns VDD = 2.0V
ns
ns
ns VDD = 2.0V
ns
 2004 Microchip Technology Inc.
Preliminary
DS39637A-page 443