PIC18F4580 Datasheet, PDF (147/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
FIGURE 10-3:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 10-4:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PORTD⁽¹⁾
LATD⁽¹⁾
TRISD⁽¹⁾
PORTE⁽¹⁾
LATE⁽¹⁾
TRISE⁽¹⁾
RD7
RD6
RD5
RD4
RD3
PORTD Data Latch Register (Read and Write to Data Latch)
PORTD Data Direction Control Register
—
—
—
—
RE3
—
—
—
—
—
IBF
OBF
IBOV PSPMODE
—
RD2
RD1
RE2
RE1
LATE Data Output bits
TRISE2 TRISE1
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP
ADCON1
—
CMCON⁽¹⁾ C2OUT
—
C1OUT
VCFG1
C2INV
VCFG0
C1INV
PCFG3
CIS
PCFG2
CM2
PCFG1
CM1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: These registers are available on PIC18F4X80 devices only.
Bit 0
RD0
RE0
TRISE0
RBIF
TMR1IF
TMR1IE
TMR1IP
PCFG0
CM0
Reset
Values
on page
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 2004 Microchip Technology Inc.
Preliminary
DS39637A-page 145