PIC18F4580 Datasheet, PDF (439/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
FIGURE 27-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
I/O pins
Note: Refer to Figure 27-4 for load conditions.
30
31
34
34
FIGURE 27-8:
BROWN-OUT RESET TIMING
VDD
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
BVDD
35
36
VBGAP = 1.2V
TABLE 27-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Sym
Characteristic
Min Typ Max Units
Conditions
30
TMCL MCLR Pulse Width (low)
2
—
—
31
TWDT Watchdog Timer Time-out Period
(no postscaler)
—
4.00 TBD
32
TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC
33
TPWRT Power-up Timer Period
—
65.5 TBD
34
TIOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—
2
—
35
TBOR Brown-out Reset Pulse Width
200
—
—
36
TIVRST Time for Internal Reference Voltage
—
20
50
to become stable
37
TLVD High/Low-Voltage Detect Pulse
Width
200
—
—
38
TCSD CPU Start-up Time
5
—
10
39
TIOBST Time for INTOSC to stabilize
—
1
—
Legend: TBD = To Be Determined
µs
ms
— TOSC = OSC1 period
ms
µs
µs VDD ≤ BVDD (see D005)
µs
µs VDD ≤ VLVD
µs
ms
 2004 Microchip Technology Inc.
Preliminary
DS39637A-page 437