PIC16F722AT-ISS Datasheet, PDF (44/286 Pages) Microchip Technology – 28-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F722A/723A
4.5.5 PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 4-5.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 4-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 7
R/W-0
CCP2IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
bit 0
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
40
OPTION_REG
RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0
23
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
41
PIE2
—
—
—
—
—
—
—
CCP2IE
42
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
43
PIR2
—
—
—
—
—
—
—
CCP2IF
44
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture,
Compare and PWM.
DS41417B-page 44
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