PIC16F722AT-ISS Datasheet, PDF (20/286 Pages) Microchip Technology – 28-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F722A/723A
TABLE 2-1: PIC16(L)F722A/723A SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Page
Bank 1
80h⁽²⁾
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx 26,34
81h
OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 23,35
82h⁽²⁾
PCL
Program Counter (PC) Least Significant Byte
0000 0000 25,34
83h⁽²⁾
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 22,34
84h⁽²⁾
FSR
Indirect Data Memory Address Pointer
xxxx xxxx 26,34
85h
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 48,35
86h
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 57,35
87h
89h
8Ah^{(1, 2)}
8Bh⁽²⁾
TRISC
TRISE
PCLATH
INTCON
TRISC7
—
—
GIE
TRISC6
—
—
PEIE
TRISC5
—
—
T0IE
TRISC4
—
TRISC3
TRISE3⁽⁵⁾
TRISC2
—
TRISC1
—
TRISC0
—
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
RBIF
1111 1111
---- 1111
---0 0000
0000 000x
67,35
74,35
25,34
40,34
8Ch
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 41,35
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE ---- ---0 42,35
8Eh
PCON
—
—
—
—
—
—
POR
BOR ---- --qq 24,35
8Fh
T1GCON
TMR1GE T1GPOL T1GTM T1GSPM T1GGO T1GVAL T1GSS1 T1GSS0 0000 0x00 113,35
DONE
90h
OSCCON
—
—
IRCF1
IRCF0
ICSL
ICSS
—
—
--10 qq-- 79,35
91h
OSCTUNE
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0 --00 0000 80,35
92h
PR2
Timer2 Period Register
93h
SSPADD⁽⁴⁾ Synchronous Serial Port (I²C™ mode) Address Register
93h
SSPMSK⁽³⁾ Synchronous Serial Port (I²C™ mode) Address Mask Register
1111 1111
0000 0000
1111 1111
115,35
165,35
176,35
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 163,35
95h
WPUB
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 57,35
96h
IOCB
IOCB7 IOCB6 IOCB5
IOCB4
IOCB3
IOCB2
IOCB1 IOCB0 0000 0000 58,35
97h
—
Unimplemented
—
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010 142,35
99h
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0 0000 0000 144,35
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
APFCON
—
—
—
—
—
—
SSSEL CCP2SEL ---- --00 47,35
9Dh
FVRCON
FVRRDY FVREN
—
—
—
—
ADFVR1 ADFVR0 q0-- --00 97,35
9Eh
—
Unimplemented
—
—
9Fh
ADCON1
—
ADCS2 ADCS1 ADCS0
—
—
ADREF1 ADREF0 0000 --00 93,35
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
These registers can be addressed from any bank.
Accessible only when SSPM<3:0> = 1001.
Accessible only when SSPM<3:0>  1001.
This bit is always ‘1’ as RE3 is input only.
DS41417B-page 20
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