PIC18F8723 Datasheet, PDF(40/60 Page) Microchip Technology – 64/80-Pin, 1-Mbit,Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology

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PIC18F8723 Datasheet, PDF (40/60 Pages) Microchip Technology – 64/80-Pin, 1-Mbit,Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology

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PIC18F8723 FAMILY

2.8 Use of the ECCP2 Trigger

An A/D conversion can be started by the Special Event

Trigger of the ECCP2 module. This requires that the

CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be

programmed as â1011â and that the A/D module is

enabled (ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, starting the A/D acquisition

and conversion, and the Timer1 (or Timer3) counter will

be reset to zero. Timer1 (or Timer3) is reset to automat-

ically repeat the A/D acquisition period with minimal

software overhead (moving ADRESH:ADRESL to the

desired location). The appropriate analog input chan-

nel must be selected and the minimum acquisition

period is either timed by the user, or an appropriate

TACQ time selected before the Special Event Trigger

sets the GO/DONE bit (starts a conversion).

If the A/D module is not enabled (ADON is cleared), the

Special Event Trigger will be ignored by the A/D module

but will still reset the Timer1 (or Timer3) counter.

TABLE 2-2: REGISTERS ASSOCIATED WITH A/D OPERATION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE TMR0IF INT0IF

RBIF

(3)

PIR1

PSPIF

ADIF

RC1IF

TX1IF SSP1IF CCP1IF TMR2IF TMR1IF

(3)

PIE1

PSPIE

ADIE

RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE

(3)

IPR1

PSPIP

ADIP

RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP

(3)

PIR2

OSCFIF CMIF

EEIF

BCL1IF HLVDIF TMR3IF CCP2IF

(3)

PIE2

OSCFIE CMIE

EEIE

BCL1IE HLVDIE TMR3IE CCP2IE

(3)

IPR2

OSCFIP CMIP

EEIP

BCL1IP HLVDIP TMR3IP CCP2IP

(3)

ADRESH A/D Result Register High Byte

(3)

ADRESL A/D Result Register Low Byte

(3)

ADCON0

CHS3

CHS2

CHS1 CHS0 GO/DONE ADON

(3)

ADCON1

VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

(3)

ADCON2 ADFM

ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0

(3)

TRISA

TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

(3)

TRISF

TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0

(3)

TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0

(3)

Legend:

Note 1:

â = unimplemented, read as â0â. Shaded cells are not used for A/D conversion.

PORTA<7:6> and their direction bits are individually configured as port pins based on various primary

oscillator modes. When disabled, these bits read as â0â.

These registers are not implemented on PIC18F6628/6723 devices.

For these Reset values, see the âPIC18F8722 Family Data Sheetâ (DS39646).

DS39894A-page 38

Preliminary

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