PIC18F8723 Datasheet, PDF (11/60 Pages) Microchip Technology – 64/80-Pin, 1-Mbit,Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology

PIC18F8723 FAMILY
FIGURE 1-1:
PIC18F6628/6723 (64-PIN) BLOCK DIAGRAM
Table Pointer<21>
Data Bus<8>
inc/dec logic
21
20
88
PCLATU PCLATH
PCU PCH PCL
Program Counter
Address Latch
Program Memory
(48/64/96/128
Kbytes)
Data Latch
8
31 Level Stack
STKPTR
Table Latch
Data Latch
Data Memory
(3.9 Kbytes)
Address Latch
12
Data Address<12>
4
BSR
12
FSR0
FSR1
FSR2
4
Access
Bank
12
inc/dec
logic
ROM Latch
Instruction Bus <16>
IR
Address
Decode
OSC1⁽³⁾
OSC2⁽³⁾
T1OSI
T1OSO
MCLR⁽²⁾
VDD, VSS
Instruction
Decode and
Control
State Machine
Control Signals
8
PRODH PRODL
Internal
Oscillator
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
3
BITOP
8
8 x 8 Multiply
8
W
8
8
8
8
ALU<8>
Precision
8
Band Gap
Reference
BOR
HLVD
ADC
12-Bit
Timer0
Timer1 Timer2
Timer3
Timer4 Comparators
PORTA
RA0:RA7⁽¹⁾
PORTB
RB0:RB7⁽¹⁾
PORTC
RC0:RC7⁽¹⁾
PORTD
RD0:RD7⁽¹⁾
PORTE
RE0:RE7⁽¹⁾
PORTF
RF0:RF7⁽¹⁾
PORTG
RG0:RG5^(1,2)
ECCP1
ECCP2 ECCP3
CCP4
CCP5 EUSART1 EUSART2 MSSP1 MSSP2
Note 1: See Table 1-2 for I/O port pin descriptions.
2: RG5 is only available when MCLR functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as
digital I/O. For additional information, refer to Section 2.0 “Oscillator Configurations” of the “PIC18F8722 Family
Data Sheet” (DS39646).
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 9