PIC18F8723 Datasheet, PDF (25/60 Pages) Microchip Technology – 64/80-Pin, 1-Mbit,Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology

PIC18F8723 FAMILY
TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number _{Pin Buffer}
TQFP
Type Type
Description
PORTD is a bidirectional I/O port.
RD0/AD0/PSP0
RD0
AD0
PSP0
72
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 0.
I/O TTL
Parallel Slave Port data.
RD1/AD1/PSP1
RD1
AD1
PSP1
69
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 1.
I/O TTL
Parallel Slave Port data.
RD2/AD2/PSP2
RD2
AD2
PSP2
68
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 2.
I/O TTL
Parallel Slave Port data.
RD3/AD3/PSP3
RD3
AD3
PSP3
67
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 3.
I/O TTL
Parallel Slave Port data.
RD4/AD4/PSP4/SDO2
66
RD4
AD4
PSP4
SDO2
I/O
ST
I/O TTL
I/O TTL
O
—
Digital I/O.
External memory address/data 4.
Parallel Slave Port data.
SPI data out.
RD5/AD5/PSP5/
SDI2/SDA2
RD5
AD5
PSP5
SDI2
SDA2
65
I/O
ST
I/O TTL
I/O TTL
I
ST
I/O I²C/SMB
Digital I/O.
External memory address/data 5.
Parallel Slave Port data.
SPI data in.
I²C™ data I/O.
RD6/AD6/PSP6/
SCK2/SCL2
RD6
AD6
PSP6
SCK2
SCL2
64
I/O
ST
I/O TTL
I/O TTL
I/O
ST
I/O I²C/SMB
Digital I/O.
External memory address/data 6.
Parallel Slave Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I²C mode.
RD7/AD7/PSP7/SS2
RD7
AD7
PSP7
SS2
63
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 7.
I/O TTL
Parallel Slave Port data.
I
TTL
SPI slave select input.
Legend:
Note 1:
2:
3:
4:
5:
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
P = Power
O
= Output
I²C™/SMB = I²C/SMBus input buffer
Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
Default assignment for ECCP2 in all operating modes (CCP2MX is set).
Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 23