PIC18LF2X Datasheet, PDF (39/44 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology

PIC18(L)F2X/4XK50
6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/
VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: 25C is recommended
Param
No.
Sym.
Characteristic
Min.
Max. Units
Conditions
D110 VIHH
D111 VDD
D111A VPEW
D111B VBULK
D112 IPP
D113 IDDP
D031 VIL
D041 VIH
D080 VOL
D090 VOH
D012 CIO
High-Voltage Programming Voltage on MCLR/VPP/RE3
Supply Voltage (VDDMIN, VDDMAX)
PIC18LF
PIC18F
Voltage during Write or Erase Operations PIC18LF
PIC18F
Voltage during Bulk Erase Operations
Programming Current on MCLR/VPP/RE3
Supply Current During Programming
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Capacitive Loading on I/O pin (PGD)
8
9
V
1.8
3.6
V
2.3
5.5
V
2.2V VDDMAX V Row Erase/Write
VDDMIN VDDMAX
2.7 VDDMAX V Bulk Erase operations
—
300 A
—
10
mA
VSS 0.2 VDD V
0.8 VDD VDD
V
—
0.6
V IOL = 8.5 mA @ 3.0V
VDD – 0.7 —
V IOH = 3.0 mA @ 3.0V
—
50
pF To meet AC
specifications
P1
TR
MCLR/VPP/RE3 Rise Time to enter Program/Verify mode
—
1.0
s (Note 1)
P2
TPGC Serial Clock (PGC) Period
100
—
ns VDD = 3.6V
1
—
s VDD = 1.8V
P2A TPGCL Serial Clock (PGC) Low Time
40
—
ns VDD = 3.6V
400
—
ns VDD = 1.8V
P2B TPGCH Serial Clock (PGC) High Time
40
—
ns VDD = 3.6V
400
—
ns VDD = 1.8V
P3
TSET1 Input Data Setup Time to Serial Clock 
15
—
ns
P4
THLD1 Input Data Hold Time from PGC
15
—
ns
P5
TDLY1 Delay between 4-bit Command and Command Operand
40
—
ns
P5A TDLY1A Delay between 4-bit Command Operand
and next 4-bit Command
40
—
ns
P6
TDLY2 Delay between Last PGC  of Command Byte to First PGC
20
 of Read of Data Word
—
ns
P9
TDLY5 PGC High Time (minimum programming
time)
1
—
ms Externally Timed
P9A TDLY5A PGC High Time
5
ms Configuration Word
programming time
P10 TDLY6 PGC Low Time after Programming
(high-voltage discharge time)
200
—
s
P11 TDLY7 Delay to allow Self-Timed Bulk Erase to PIC18(L)FX5K50 15
occur
PIC18(L)FX6K50
—
ms
PIC18(L)F24K50
12
—
ms
P11A TDRWT Data Write Polling Time
4
—
ms
Note 1:
Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program executions
to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only) + 1.5
s (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the
oscillator period. For specific values, refer to the Electrical Characteristics section of the device data sheet for the
particular device.
 2012 Microchip Technology Inc.
DS41630B-page 39