PIC18LF2X Datasheet, PDF(24/44 Page) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology

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PIC18LF2X Datasheet, PDF (24/44 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology

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PIC18(L)F2X/4XK50

4.0 READING THE DEVICE

4.1 Read Code Memory, ID Locations

and Configuration Bits

Code memory is accessed one byte at a time via the

4-bit command, â1001â (table read, post-increment).

The contents of memory pointed to by the Table Pointer

(TBLPTRU:TBLPTRH:TBLPTRL) are serially output on

PGD.

The 4-bit command is shifted in LSb first. The read is

executed during the next 8 clocks, then shifted out on

PGD during the last 8 clocks, LSb to MSb. A delay of

P6 must be introduced after the falling edge of the 8th

PGC of the operand to allow PGD to transition from an

input to an output. During this time, PGC must be held

low (see Figure 4-1). This operation also increments

the Table Pointer by one, pointing to the next byte in

code memory for the next read.

This technique will work to read any memory in the

000000h to 3FFFFFh address space, so it also applies

to the reading of the ID and Configuration registers.

Note:

When table read protection is enabled, the

first read access to a protected block

should be discarded and the read

repeated to retrieve valid data.

Subsequent reads of the same block can

be performed normally.

TABLE 4-1: READ CODE MEMORY SEQUENCE

4-bit

Command

Data Payload

Step 1: Set Table Pointer.

0000

0E <Addr[21:16]>

6E F8

0E <Addr[15:8]>

6E F7

0E <Addr[7:0]>

6E F6

MOVLW Addr[21:16]

MOVWF TBLPTRU

MOVLW <Addr[15:8]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Step 2: Read memory and then shift out on PGD, LSb to MSb.

1001

00 00

TBLRD *+

Core Instruction

FIGURE 4-1:

TABLE READ POST-INCREMENT INSTRUCTION TIMING DIAGRAM (1001)

PGC

PGD

1234

12 3 45 6 78

9 10 11 12 13 14 15 16

12 34

P5A

P14

1001

LSb 1 2 3 4 5 6

(Note 1)

MSb n n n n

PGD = Input

Shift Data Out

PGD = Output

Fetch Next 4-bit Command

PGD = Input

Note 1: Magnification of the high-impedance delay between PGC and PGD is shown in Figure 4-6.

DS41630B-page 24

ï£ 2012 Microchip Technology Inc.

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