PIC18LF2X Datasheet, PDF(28/44 Page) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology

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PIC18LF2X Datasheet, PDF (28/44 Pages) Microchip Technology – 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology

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PIC18(L)F2X/4XK50

5.0 CONFIGURATION WORD

The PIC18(L)F2X/4XK50 devices have several

Configuration Words. These bits can be set or cleared

to select various device configurations. All other mem-

ory areas should be programmed and verified prior to

setting Configuration Words. These bits may be read

out normally, even after read or code protection. See

Table 5-1 for a list of Configuration bits and device IDs,

and Table 5-3 for the Configuration bit descriptions.

5.1 User ID Locations

A user may store identification information (ID) in eight

ID locations mapped in 200000h:200007h. It is

recommended that the Most Significant nibble of each

ID be Fh. In doing so, if the user code inadvertently tries

to execute from the ID space, the ID data will execute

as a NOP.

5.2 Device ID Word

The device ID word for the PIC18(L)F2X/4XK50

devices is located at 3FFFFEh:3FFFFFh. These bits

may be used by the programmer to identify what device

type is being programmed and read out normally, even

after code or read protection. See Table 5-2 for a

complete list of device ID values.

FIGURE 5-1:

READ DEVICE ID WORD

FLOW

Start

Set TBLPTR = 3FFFFE

Read Low Byte

with Post-Increment

Read High Byte

with Post-Increment

Done

TABLE 5-1: CONFIGURATION BITS AND DEVICE IDs

File Name

Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default/

Unprogrammed

Value

300000h CONFIG1L â

USBLSDIV CPUDIV1 CPUDIV0

PLLEN(3) PLLMULT(3) --00 0-00

300001h CONFIG1H IESO FCMEN PCLKEN

FOSC3 FOSC2 FOSC1

FOSC0

001- 0101

300002h CONFIG2L â LPBOR

BORV1 BORV0 BOREN1 BOREN0 PWRTEN -1-1 1111

300003h CONFIG2H â

WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN1 WDTEN0 --11 1111

300005h CONFIG3H MCLRE SDOMX

T3CMX

PBADEN CCP2MX

11-1 --11

300006h CONFIG4L DEBUG XINST

300008h CONFIG5L â

ICPRT

LVP

STVREN

101- -1-1

CP3(1)

CP2(1)

CP1

CP0

---- 1111

300009h CONFIG5H CPD CPB

30000Ah CONFIG6L â

11-- ----

WRT3(1) WRT2(1) WRT1

WRT0

---- 1111

30000Bh CONFIG6H WRTD WRTB

30000Ch CONFIG7L â

WRTC

111- ----

EBTR3(1) EBTR2(1) EBTR1

EBTR0

---- 1111

30000Dh CONFIG7H

3FFFFEh DEVID1(2)

3FFFFFh DEVID2(2)

DEV2

DEV10

EBTRB

DEV1

DEV9

DEV0

DEV8

REV4

DEV7

REV3

DEV6

REV2

DEV5

REV1

DEV4

REV0

DEV3

-1-- ----

See Table 5-2

Legend:

Note 1:

x = unknown, u = unchanged, â = unimplemented. Shaded cells are unimplemented, read as â0â.

These bits are only implemented on specific devices. Refer to Section 2.4 âMemory Mapsâ to determine which bits apply based

on available memory.

DEVID registers are read-only and cannot be programmed by the user.

When the 3x Multiplier mode is selected, the input frequency has to be 16 MHz. When the 4x Multiplier mode is selected, the

input frequency has to be between 8 MHz and 16 MHz.

DS41630B-page 28

ï£ 2012 Microchip Technology Inc.

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