MIC24045 Datasheet, PDF (36/46 Pages) Microchip Technology – I2C Programmable, 4.5V-19V Input, 5A Step-Down Converter

MIC24045
Note:
Writing to a non-existing register location
will generate a reject action (NACK) by the
MIC24045 after the command byte.
8.5.2
SINGLE WRITE WITH REPEATED
START (Sr)
In multi-master I²C systems, this bus transaction is the
recommended method to execute V_OUT on-the-fly
changes in multiple steps.
The sequence is the same as for the previous Single
Write transaction, except that at the end the master
issues a Repeated START (Sr) instead of a STOP (P),
and another (or more) Single Write operation takes
place until the master releases the bus with a STOP.
This way the master does not release the bus after the
first Single Write and can accomplish the V_OUT
on-the-fly change in multiple steps, without interference
from other master devices.
The Single Write with Repeated Start (Sr) command is
as follows and it is illustrated in the timing diagram of
Figure 8-4 below:
1. Send START sequence
2. Send 7-bit slave address
3. Send the R/W bit - 0 to indicate a write operation
4. Wait for acknowledge from the slave
5. Send the command byte – address that needs to
be written
6. Wait for acknowledge from the slave
7. Receive the 8-bit data – DATA 1 from the master
and write it to the slave register indicated in step
5, starting from MSB
8. Acknowledge from the slave – The register is
updated with DATA 1
9. Send START sequence
10. Send 7-bit slave address
11. Send the R/W bit - 0 to indicate a write operation
12. Wait for acknowledge from the slave
13. Send the command byte – address that needs to
be written
14. Wait for acknowledge from the slave
15. Receive the 8-bit data – DATA 2 from the master
and write it to the slave register indicated in
step 13, starting from MSB
16. Acknowledge from the slave – The register is
updated with DATA 2
These steps (steps 9 through 16) can continue as many
times as needed to write to the same register (or
another valid writable register as indicated in steps 5
and 13) without sending a STOP sequence. The
master will conclude the data transfer on the last write
operation by generating a STOP condition.
SCL
123456789
Slave address
Command byte
SDA S
0A00
Register address
A
DATA 1
START
R/W ACK from Slave
ACK from Slave
SCL
123456789
Slave address
Command byte
SDA Sr
0A00
Register Address
Repeated
START
R/W ACK from Slave
SCL
123456789
Slave address
Command byte
SDA Sr
0A00
Register Address
Repeated
START
R/W ACK from Slave
A
DATA 2
ACK from Slave
A
DATA N
ACK from Slave
FIGURE 8-4:
Single Write with Repeated Start Timing Diagram.
Note:
Writing to a non-existing register location
will generate a reject action (NACK) by the
MIC24045 after the command byte.
A
ACK from Slave
A
ACK from Slave
AP
ACK
from
Slave
STOP
DS20005568A-page 36
 2016 Microchip Technology Inc.