MIC24045 Datasheet, PDF (35/46 Pages) Microchip Technology – I2C Programmable, 4.5V-19V Input, 5A Step-Down Converter

8.3 Device Address
The MIC24045 device uses a 7-bit address, which is
set in hardware, using three-state pins ADR0 and
ADR1 (HIGH, LOW, or high-Z). These two three-state
pins allow for nine different addresses, as described in
Table 8-1 below.
TABLE 8-1:
ADR1
MIC24045 I²C ADDRESS
SETTING
ADR0
I²C Address
0
0
1
1
0
high-Z
1
high-Z
high-Z
0
1
0
1
high-Z
0
high-Z
1
high-Z
101 0000
101 0001
101 0010
101 0011
101 0100
101 0101
101 0110
101 0111
101 1000
8.4 Acknowledge
The number of data bytes transferred between the
START and the STOP conditions, from transmitter to
receiver, is not limited. Each byte of eight bits is fol-
lowed by one Acknowledge bit. The Acknowledge bit is
a HIGH level put on the bus by the transmitter, whereas
the master generates an extra acknowledge-related
clock pulse. The device that acknowledges has to pull
down the SDA line during the acknowledge clock pulse,
so that the SDA line is stable LOW during the HIGH
period of the acknowledge-related clock pulse; setup
and hold times must be taken into account.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte.
Also, a master receiver must generate an acknowledge
after the reception of each byte that has been clocked
out of the slave transmitter, except on the last received
byte. A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on
the last byte that has been clocked out of the slave
MIC24045
transmitter. In this event, the transmitter must leave the
data line HIGH to enable the master to generate a
STOP condition.
8.5 Bus transactions
8.5.1 SINGLE WRITE
The first seven bits of the first byte make up the slave
address. The eighth bit is the LSB (Least Significant
bit). It determines the direction of the message (R/W).
A ‘zero’ in the least significant position of the first byte
means that the master will write information to a
selected slave. A ‘1’ in this position means that the
master will read information from the slave. When an
address is sent, each device in a system compares the
first seven bits after the START condition with its
address. If they match, the device considers itself
addressed by the master as a slave-receiver or
slave-transmitter, depending on the R/W bit.
Command byte is a data byte which selects a register
on the device. The Least Significant six bits of the com-
mand byte determine the address of the register that
needs to be written.
The data to port is the 8-bit data that needs to be written
to the selected register. This is followed by the
acknowledge from the slave and then the STOP condi-
tion.
The Write command is as follows and it is illustrated in
the timing diagram below:
1. Send START sequence
2. Send 7-bit slave address
3. Send the R/W bit - 0 to indicate a write operation
4. Wait for acknowledge from the slave
5. Send the command byte – address that needs to
be written
6. Wait for acknowledge from the slave
7. Receive the 8-bit data from the master and write
it to the slave register indicated in step 5 starting
from MSB
8. Acknowledge from the slave
9. Send STOP sequence
SCL ^{1 2 3 4 5 6 7 8 9}
Slave address
Command byte
SDA S
0A00
START condition
R/W ACK from
Slave
A
ACK from
Slave
Data to port
DATA 1
AP
ACK from
Slave
Data out from port
FIGURE 8-3:
Single Write Timing Diagram.
 2016 Microchip Technology Inc.
DATA 1 VALID
DS20005568A-page 35