MIC24045 Datasheet, PDF (20/46 Pages) Microchip Technology – I2C Programmable, 4.5V-19V Input, 5A Step-Down Converter

MIC24045
4.12 Overcurrent Protection
The MIC24045 features instantaneous cycle-by-cycle
current limit with current sensing both on the low-side
and high-side switches. It also offers a Hiccup mode for
prolonged overloads or short-circuit conditions.
Low-side cycle-by-cycle protection detects the current
level of the inductor current during the low-side MOS-
FET ON time. The high-side MOSFET turn-on is inhib-
ited as long as the low-side MOSFET current limit is
above the low-side current-limit threshold level. The
inductor current will continue decaying until the current
falls below the threshold, then the high-side MOSFET
will be enabled again according to the duty cycle
requirement from the PWM modulator.
The mechanism is illustrated in Figure 4-1.
Low-Side
Current-Limit
Threshold
Resulting
Duty Cycle
LS OC Detected
HS Turn-on
I_L
Inhibited
LS Current OK
HS Turn-on
is Enabled
LS OC Detected
HS Turn-on
Inhibited
¨I_Lpp
I_OUT
Required
Duty Cycle
Valley CM clock
(HS OFF, LS ON)
Time
FIGURE 4-1:
Low-Side Cycle-by-Cycle Current-Limit Action.
The low-side current limit is programmable at four
different levels (for 2A, 3A, 4A and 5A loads) in order to
optimize inductor size for different application
requirements. These levels are listed in Section 5.0
“Registers Maps and I2C Programmability”.
Since the low-side current limit acts on the valley cur-
rent, the DC output current level (I_OUT), where the
low-side cycle-by-cycle current limit is engaged, will be
higher than the current limit value by an amount equal
to IL_PP/2, where IL_PP is the peak-to-peak inductor
ripple current.
The high-side current limit is approximately 1.4 – 1.5
times greater than the low-side current limit (typical val-
ues). The high-side cycle-by-cycle current limit immedi-
ately truncates the high-side ON time without waiting
for the OFF clocking event.
A leading edge blanking (LEB) timer (108 ns, typical) is
provided on the high-side cycle-by-cycle current limit to
mask the switching noise and to prevent falsely trigger-
ing the protection. High-side cycle-by-cycle current
limit action cannot take place before the LEB timer
expires.
0000 and above 1111. High-side current limit events
do not increment the counter. Only detections from
low-side current limit events trigger the counter.
If the counter reaches 1111 (or 15 events), the high
and low-side MOSFETs become tri-stated and power
delivery to the output is inhibited for a duration which is
dependent on the soft-start rate and can be calculated
with the following equation:
EQUATION 4-1:
Inhibited Time = --1---3---.--5---V----
SS_SRx
Where
SS_SRx = selected soft-start rate
(SS_SRx = SS_SR0, SS_SR1, SS_SR2
or SS_SR3).
See Electrical Characteristics table.
This digital integration mechanism provides immunity
to the momentary overloading of the output. After the
wait time, the MIC24045 retries entering operation and
initiates a new soft-start sequence.
Hiccup mode protection reduces power dissipation in
permanent short-circuit conditions. On each clock
cycle, where a low-side cycle-by-cycle current-limit
event is detected, a 4-bit up/down counter is incre-
mented. On each clock cycle, without a concurrent
low-side current limit event, the counter is decremented
or left at zero. The counter cannot wrap-around below
Note that Hiccup mode short-circuit protection is active
at all times, including the soft-start ramp. In case of very
large output capacitors, consider slowing down the
soft-start slew rate to prevent start-up problems, espe-
cially if the load is completely discharging the output
capacitor during the hiccup wait time.
DS20005568A-page 20
 2016 Microchip Technology Inc.