MIC24045 Datasheet, PDF (16/46 Pages) Microchip Technology – I2C Programmable, 4.5V-19V Input, 5A Step-Down Converter

MIC24045
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
MIC24045
1, 2
3, 4, 13
5, 6
7
Symbol
V_IN
P_GND
LX
BST
8
PG
9
ADR0
10
ADR1
11
SCL
12
SDA
14
A_GND
15
COMP
16
OUTSNS
17
EN
18
V_DDA
19
V_DDP
20
V_INLDO
21
V_{IN_}EP
22
P_{GND_}EP
23
LX_EP
Pin Function
Input Voltage Pin
Power Ground Pin
Switch Node Pin
Bootstrap Capacitor Pin. A bootstrap capacitor is connected
between the BST and LX pins.
Power Good Open-Drain Output Pin
I²C Address Programming Pin 0
I²C Address Programming Pin 1
I²C Clock Input Pin
I²C Data Input/Output Pin
Analog Ground Pin
Transconductance Error Amplifier Output Pin. Connect the com-
pensation network from COMP to A_GND.
Output Sensing Pin
Precision Enable Input Pin
Internal Regulator Output Pin
MOSFET Drivers Internal Supply Pin
Internal Regulator Input Pin
V_IN Exposed Pad. Electrically connected to V_IN.
P_GND Exposed Pad. Electrically connected to P_GND.
LX Exposed Pad. Electrically connected to LX.
3.1 Input Voltage Pin (V_IN)
Input Voltage pin for the Buck converter power stage.
These pins are the drain terminal of the internal
high-side N-channel MOSFET. A 10 µF minimum
ceramic capacitor should be connected from V_IN to the
P_GND pins as close as possible to the device. A combi-
nation of multiple ceramic capacitors of different sizes
is recommended.
3.2 Power Ground Pin (P_GND)
Low-side MOSFET source terminal and low-side driver
return. Connect the ceramic input capacitors to P_GND
as close as possible to the device.
3.3 Switch Node Pin (LX)
Drain (low-side MOSFET) and source (high-side
MOSFET) connection of the internal power N-channel
FETs. The external inductor (switched side) and
bootstrap capacitor (bottom terminal) must be
connected to these pins.
3.4 Bootstrap Capacitor Pin (BST)
Supply voltage for the driver of the high-side N-channel
power MOSFET. Connect the bootstrap capacitor (top
terminal) to this pin.
3.5 Power Good Output Pin (PG)
When the output voltage is within 92.5% of the nominal
set point, this pin will go from logic low to logic high
through an external pull-up resistor. This pin is the drain
connection of an internal N-channel FET.
3.6 I²C Address Programming Pin 0
(ADR0)
Three-state pin (low, high and high-Z) for I²C address
programming. Together with ADR1, ADR0 defines nine
logic values corresponding to nine I²C addresses.
3.7 I²C Address Programming Pin 1
(ADR1)
Three-state pin (low, high and high-Z) for I²C address
programming. Together with ADR0, ADR1 defines nine
logic values corresponding to nine I²C addresses.
DS20005568A-page 16
 2016 Microchip Technology Inc.