PIC16LF1946_13 Datasheet, PDF (334/478 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC16(L)F1946/47
REGISTER 26-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
U-0
—
bit 7
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
CPSCH<4:0>
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
CPSCH<4:0>: Capacitive Sensing Channel Select bits
If CPSON = 0:
These bits are ignored. No channel is selected.
If CPSON = 1:
00000 = channel 0, (CPS0)
00001 = channel 1, (CPS1)
00010 = channel 2, (CPS2)
00011 = channel 3, (CPS3)
00100 = channel 4, (CPS4)
00101 = channel 5, (CPS5)
00110 = channel 6, (CPS6)
00111 = channel 7, (CPS7)
01000 = channel 8, (CPS8)
01001 = channel 9, (CPS9)
01010 = channel 10, (CPS10)
01011 = channel 11, (CPS11)
01100 = channel 12, (CPS12)
01101 = channel 13, (CPS13)
01110 = channel 14, (CPS14)
01111 = channel 15, (CPS15)
10000 = channel 16, (CPS16)
10001 = Reserved. Do not use.
.
.
.
11111 = Reserved. Do not use.
TABLE 26-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
—
—
ANSA5 ANSA4 ANSA3 ANSA2 ANSA1
CPSCON0
CPSON CPSRM
—
—
CPSRNG<1:0>
CPSOUT
CPSCON1
—
—
—
CPSCH<4:0>
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE
PSA
PS2
PS1
T1CON
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN T1SYNC
—
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1
TRISD
TRISD<7:0>
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the CPS module.
ANSA0
T0XCS
PS0
TMR1ON
TRISA0
TRISB0
Register
on Page
132
333
334
197
207
131
134
140
DS41414D-page 334
 2010-2012 Microchip Technology Inc.