PIC16LF1946_13 Datasheet, PDF (106/478 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC16(L)F1946/47
9.1.1 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction
- SLEEP instruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
cleared.
• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction
- SLEEP instruction will be completely exe-
cuted
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
FIGURE 9-1:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
OSC1⁽¹⁾
CLKOUT⁽²⁾
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOST⁽³⁾
Interrupt flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
PC
Instruction
Fetched
Inst(PC) = Sleep
Instruction
Executed
Inst(PC - 1)
Processor in
Sleep
PC + 1
Inst(PC + 1)
Sleep
PC + 2
Interrupt Latency⁽⁴⁾
PC + 2
Inst(PC + 2)
Inst(PC + 1)
PC + 2
Forced NOP
0004h
Inst(0004h)
Forced NOP
0005h
Inst(0005h)
Inst(0004h)
Note 1:
2:
3:
4:
XT, HS or LP Oscillator mode assumed.
CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.
TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
IOCBF
IOCBN
IOCBP
PIE1
PIE2
PIE3
PIE4
PIR1
PIR2
PIR3
PIR4
STATUS
WDTCON
Legend:
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
OSFIE
C2IE
C1IE
EEIE
BCLIE
LCDIE
C3IE
—
CCP5IE
CCP4IE
CCP3IE
TMR6IE
—
TMR4IE
—
—
RC2IE
TX2IE
—
—
BCL2IE
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
OSFIF
C2IF
C1IF
EEIF
BCLIF
LCDIF
C3IF
—
CCP5IF
CCP4IF
CCP3IF
TMR6IF
—
TMR4IF
—
—
RC2IF
TX2IF
—
—
BCL2IF
—
—
—
TO
PD
Z
DC
—
—
WDTPS<4:0>
— = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.
IOCIF
IOCBF0
IOCBN0
IOCBP0
TMR1IE
CCP2IE
—
SSP2IE
TMR1IF
CCP2IF
—
SSP2IF
C
SWDTEN
Register on
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DS41414D-page 106
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