PIC24FJ256GB210 Datasheet, PDF (330/386 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB210 FAMILY
26.2 On-Chip Voltage Regulator
All PIC24FJ256GB210 family devices power their core
digital logic at a nominal 1.8V. This may create an issue
for designs that are required to operate at a higher
typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC24FJ256GB210 family
incorporate an on-chip regulator that allows the device
to run its core logic from VDD.
The regulator is controlled by the ENVREG pin. Tying VDD
to the pin enables the regulator, which in turn, provides
power to the core from the other VDD pins. When the reg-
ulator is enabled, a low-ESR capacitor (such as ceramic)
must be connected to the VCAP pin (Figure 26-1). This
helps to maintain the stability of the regulator. The recom-
mended value for the filter capacitor (CEFC) is provided in
Section 29.1 “DC Characteristics”.
26.2.1
VOLTAGE REGULATOR
LOW-VOLTAGE DETECTION
When the on-chip regulator is enabled, it provides a
constant voltage of 1.8V nominal to the digital core
logic.
The regulator can provide this level from a VDD of about
2.1V, all the way up to the device’s VDDMAX. It does not
have the capability to boost VDD levels. In order to pre-
vent “brown-out” conditions when the voltage drops too
low for the regulator, the Brown-out Reset occurs. Then
the regulator output follows VDD with a typical voltage
drop of 300 mV.
To provide information about when the regulator
voltage starts reducing, the on-chip regulator includes
a simple Low-Voltage Detect circuit, which sets the
Low-Voltage Detect Interrupt Flag, LVDIF (IFS4<8>).
This can be used to generate an interrupt to trigger an
orderly shutdown.
FIGURE 26-1:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
Regulator Enabled (ENVREG tied to VDD):
3.3V⁽¹⁾
PIC24FJXXXGB2XX
VDD
ENVREG
CEFC
(10 F typ)
VCAP
VSS
Note 1:
This is a typical operating voltage. Refer to
Section 29.1 “DC Characteristics” for
the full operating ranges of VDD.
26.2.2 ON-CHIP REGULATOR AND POR
When the voltage regulator is enabled, it takes approx-
imately 10 s for it to generate output. During this time,
designated as TVREG, code execution is disabled.
TVREG is applied every time the device resumes
operation after any power-down, including Sleep mode.
TVREG is determined by the status of the VREGS bit
(RCON<8>) and the WUTSEL Configuration bits
(CW3<11:10>). Refer to Section 29.0 “Electrical
Characteristics” for more information on TVREG.
26.2.3 ON-CHIP REGULATOR AND BOR
When the on-chip regulator is enabled,
PIC24FJ256GB210 family devices also have a simple
brown-out capability. If the voltage supplied to the reg-
ulator is inadequate to maintain the output level, the
regulator Reset circuitry will generate a Brown-out
Reset. This event is captured by the BOR (RCON<1>)
flag bit. The brown-out voltage specifications are
provided in Section 7. “Reset” (DS39712) in the
“PIC24F Family Reference Manual”.
Note:
For more information, see Section 29.0
“Electrical Characteristics”. The infor-
mation in this data sheet supersedes the
information in the FRM.
26.2.4
VOLTAGE REGULATOR STANDBY
MODE
When enabled, the on-chip regulator always consumes
a small incremental amount of current over IDD/IPD,
including when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator can be made to
enter Standby mode on its own whenever the device
goes into Sleep mode. This feature is controlled by the
VREGS bit (RCON<8>). Clearing the VREGS bit
enables the Standby mode. When waking up from
Standby mode, the regulator needs to wait for TVREG to
expire before wake-up.
The regulator wake-up time required for Standby
mode is controlled by the WUTSEL<1:0>
(CW3<11:10>) Configuration bits. The regulator
wake-up time is lower when WUTSEL<1:0> = 01, and
higher when WUTSEL<1:0> = 11. Refer to the TVREG
specification in Table 29-10 for regulator wake-up
time.
When the regulator’s Standby mode is turned off
(VREGS = 1), the device wakes up without waiting for
TVREG. However, with the VREGS bit set, the power
consumption while in Sleep mode will be approximately
40 A higher than what it would be if the regulator was
allowed to enter Standby mode.
DS39975A-page 330
 2010 Microchip Technology Inc.