PIC24FJ256GB210 Datasheet, PDF (145/386 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB210 FAMILY
FIGURE 8-2:
96 MHz PLL BLOCK
FNOSC<2:0>
Input from
POSC
Input from
FRC
(4 MHz or
8 MHz)
PLLDIV<2:0>
 12
8
6
5
4
3
2
1
111
110
101
100 4 MHz
011
010
001
000
96 MHz
PLL
2
32 MHz
3
48 MHz Clock
for USB Module
 8 ₁₁
4
2
10
01
1
00
PLL Output
for System Clock
CPDIV<1:0>
8.5.1 SYSTEM CLOCK GENERATION
The system clock is generated from the 96 MHz branch
using a configurable postscaler/divider to generate a
range of frequencies for the system clock multiplexer.
The output of the multiplexer is further passed through
a fixed divide-by-3 divider and the final output is used
as the system clock. Figure 8-2 shows this logic in the
system clock sub-block. Since the source is a 96 MHz
signal, the possible system clock frequencies are listed
in Table 8-2. The available system clock options are
always the same, regardless of the setting of the
PLLDIV Configuration bits.
TABLE 8-2: SYSTEM CLOCK OPTIONS FOR 96 MHz PLL BLOCK
MCU Clock Division
(CPDIV<1:0>)
System Clock Frequency
(Instruction Rate in MIPS)
Note 1:
None (00)
32 MHz (16)
2 (01)
4 (10)
8 (11)
16 MHz (8)
8 MHz (4)⁽¹⁾
4 MHz (2)⁽¹⁾
These options are not compatible with USB operation. They may be used whenever the PLL branch is
selected and the USB module is disabled.
 2010 Microchip Technology Inc.
DS39975A-page 145