PIC24FJ256GB210 Datasheet, PDF (16/386 Pages) Microchip Technology – 64/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB210 FAMILY
1.2 USB On-The-Go
The USB On-The-Go (USB OTG) module provides
on-chip functionality as a target device, compatible with
the USB 2.0 standard, as well as limited stand-alone
functionality as a USB embedded host. By implement-
ing USB Host Negotiation Protocol (HNP), the module
can also dynamically switch between device and host
operation, allowing for a much wider range of versatile
USB enabled applications on a microcontroller
platform.
In addition to USB host functionality,
PIC24FJ256GB210 family devices provide a true
single chip USB solution, including an on-chip
transceiver and voltage regulator, and a voltage boost
generator for sourcing bus power during host
operations.
1.3 Other Special Features
• Peripheral Pin Select: The Peripheral Pin Select
(PPS) feature allows most digital peripherals to be
mapped over a fixed set of digital I/O pins. Users
may independently map the input and/or output of
any one of the many digital peripherals to any one
of the I/O pins.
• Communications: The PIC24FJ256GB210 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There are three independent I²C™
modules that support both Master and Slave
modes of operation. Devices also have, through
the PPS feature, four independent UARTs with
built-in IrDA^® encoders/decoders and three SPI
modules.
• Analog Features: All members of the
PIC24FJ256GB210 family include a 10-bit A/D
Converter (ADC) module and a triple comparator
module. The ADC module incorporates program-
mable acquisition time, allowing for a channel to
be selected and a conversion to be initiated
without waiting for a sampling period, and faster
sampling speeds. The comparator module
includes three analog comparators that are
configurable for a wide range of operations.
• CTMU Interface: In addition to their other analog
features, members of the PIC24FJ256GB210
family include the CTMU interface module. This
provides a convenient method for precision time
measurement and pulse generation, and can
serve as an interface for capacitive sensors.
• Enhanced Parallel Master/Parallel Slave Port:
There are general purpose I/O ports, which can
be configured for parallel data communications. In
this mode, the device can be master or slave on
the communication bus. 4-bit, 8-bit and 16-bit data
transfers, with up to 23 external address lines, are
supported in Master modes.
• Real-Time Clock and Calendar: (RTCC) This
module implements a full-featured clock and
calendar with alarm functions in hardware, freeing
up timer resources and program memory space
for use of the core application.
1.4 Details on Individual Family
Members
Devices in the PIC24FJ256GB210 family are available
in 64-pin and 100-pin packages. The general block
diagram for all devices is shown in Figure 1-1.
The devices are differentiated from each other in seven
ways:
1. Flash program memory (128 Kbytes for
PIC24FJ128GB2XX devices and 256 Kbytes
for PIC24FJ256GB2XX devices).
2. Available I/O pins and ports (52 pins on 6 ports
for PIC24FJXXXGB2XX devices and 84 pins on
7 ports for PIC24FJXXXGB2XX devices).
3. Available Interrupt-on-Change Notification (ICN)
inputs (52 on PIC24FJXXXGB2XX devices and
84 on PIC24FJXXXGB2XX devices).
4. Available remappable pins (29 pins on
PIC24FJXXXGB2XX devices and 44 pins on
PIC24FJXXXGB2XX devices).
5. Analog channels for ADC (16 channels for
PIC24FJXXXGB206 devices and 24 channels
for PIC24FJXXXGB2XX devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1 and Table 1-2.
A list of the pin features available on the
PIC24FJ256GB210 family devices, sorted by function,
is shown in Table 1-1. Note that this table shows the pin
location of individual peripheral features and not how
they are multiplexed on the same pin. This information
is provided in the pinout diagrams in the beginning of
the data sheet. Multiplexed features are sorted by the
priority given to a feature, with the highest priority
peripheral being listed first.
DS39975A-page 16
 2010 Microchip Technology Inc.