PIC24FJ256GB106-I Datasheet, PDF (291/328 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB110 FAMILY
TABLE 27-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
Assembly Syntax
Description
# of
# of
Status Flags
Words Cycles
Affected
GOTO
INC
INC2
IOR
LNK
LSR
MOV
MUL
NEG
NOP
POP
PUSH
GOTO
GOTO
INC
INC
INC
INC2
INC2
INC2
IOR
IOR
IOR
IOR
IOR
LNK
LSR
LSR
LSR
LSR
LSR
MOV
MOV
MOV
MOV
MOV
MOV.b
MOV
MOV
MOV
MOV
MOV.D
MOV.D
MUL.SS
MUL.SU
MUL.US
MUL.UU
MUL.SU
MUL.UU
MUL
NEG
NEG
NEG
NOP
NOPR
POP
POP
POP.D
POP.S
PUSH
PUSH
PUSH.D
PUSH.S
Expr
Wn
f
f,WREG
Ws,Wd
f
f,WREG
Ws,Wd
f
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
#lit14
f
f,WREG
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,Wn
[Wns+Slit10],Wnd
f
f,WREG
#lit16,Wn
#lit8,Wn
Wn,f
Wns,[Wns+Slit10]
Wso,Wdo
WREG,f
Wns,Wd
Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,#lit5,Wnd
Wb,#lit5,Wnd
f
f
f,WREG
Ws,Wd
f
Wdo
Wnd
f
Wso
Wns
Go to Address
2
Go to Indirect
1
f=f+1
1
WREG = f + 1
1
Wd = Ws + 1
1
f=f+2
1
WREG = f + 2
1
Wd = Ws + 2
1
f = f .IOR. WREG
1
WREG = f .IOR. WREG
1
Wd = lit10 .IOR. Wd
1
Wd = Wb .IOR. Ws
1
Wd = Wb .IOR. lit5
1
Link Frame Pointer
1
f = Logical Right Shift f
1
WREG = Logical Right Shift f
1
Wd = Logical Right Shift Ws
1
Wnd = Logical Right Shift Wb by Wns
1
Wnd = Logical Right Shift Wb by lit5
1
Move f to Wn
1
Move [Wns+Slit10] to Wnd
1
Move f to f
1
Move f to WREG
1
Move 16-bit Literal to Wn
1
Move 8-bit Literal to Wn
1
Move Wn to f
1
Move Wns to [Wns+Slit10]
1
Move Ws to Wd
1
Move WREG to f
1
Move Double from W(ns):W(ns+1) to Wd
1
Move Double from Ws to W(nd+1):W(nd)
1
{Wnd+1, Wnd} = Signed(Wb) * Signed(Ws)
1
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws)
1
{Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws)
1
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5)
1
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1
W3:W2 = f * WREG
1
f=f+1
1
WREG = f + 1
1
Wd = Ws + 1
1
No Operation
1
No Operation
1
Pop f from Top-of-Stack (TOS)
1
Pop from Top-of-Stack (TOS) to Wdo
1
Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1
Pop Shadow Registers
1
Push f to Top-of-Stack (TOS)
1
Push Wso to Top-of-Stack (TOS)
1
Push W(ns):W(ns+1) to Top-of-Stack (TOS)
1
Push Shadow Registers
1
2 None
2 None
1 C, DC, N, OV, Z
1 C, DC, N, OV, Z
1 C, DC, N, OV, Z
1 C, DC, N, OV, Z
1 C, DC, N, OV, Z
1 C, DC, N, OV, Z
1 N, Z
1 N, Z
1 N, Z
1 N, Z
1 N, Z
1 None
1 C, N, OV, Z
1 C, N, OV, Z
1 C, N, OV, Z
1 N, Z
1 N, Z
1 None
1 None
1 N, Z
1 N, Z
1 None
1 None
1 None
1
1 None
1 N, Z
2 None
2 None
1 None
1 None
1 None
1 None
1 None
1 None
1 None
1 C, DC, N, OV, Z
1 C, DC, N, OV, Z
1 C, DC, N, OV, Z
1 None
1 None
1 None
1 None
2 None
1 All
1 None
1 None
2 None
1 None
© 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 289