PIC24FJ256GB106-I Datasheet, PDF (157/328 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB110 FAMILY
12.0 INPUT CAPTURE WITH
DEDICATED TIMERS
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 34. “Input Capture with
Dedicated Timer” (DS39722).
Devices in the PIC24FJ256GB110 family all feature
9 independent input capture modules. Each of the
modules offers a wide range of configuration and oper-
ating options for capturing external pulse events and
generating interrupts.
Key features of the input capture module include:
• Hardware-configurable for 32-bit operation in all
modes by cascading two adjacent modules
• Synchronous and Trigger modes of output
compare operation, with up to 30 user-selectable
trigger/sync sources available
• A 4-level FIFO buffer for capturing and holding
timer values for several events
• Configurable interrupt generation
• Up to 6 clock sources available for each module,
driving a separate internal 16-bit counter
The module is controlled through two registers,
ICxCON1 (Register 12-1) and ICxCON2
(Register 12-2). A general block diagram of the module
is shown in Figure 12-1.
12.1 General Operating Modes
12.1.1 SYNCHRONOUS AND TRIGGER
MODES
By default, the input capture module operates in a
free-running mode. The internal 16-bit counter ICxTMR
counts up continuously, wrapping around from FFFFh
to 0000h on each overflow, with its period synchronized
to the selected external clock source. When a capture
event occurs, the current 16-bit value of the internal
counter is written to the FIFO buffer.
In Synchronous mode, the module begins capturing
events on the ICx pin as soon as its selected clock
source is enabled. Whenever an event occurs on the
selected sync source, the internal counter is reset. In
Trigger mode, the module waits for a Sync event from
another internal module to occur before allowing the
internal counter to run.
Standard, free-running operation is selected by setting
the SYNCSEL bits to ‘00000’, and clearing the ICTRIG
bit (ICxCON2<7>). Synchronous and Trigger modes
are selected any time the SYNCSEL bits are set to any
value except ‘00000’. The ICTRIG bit selects either
Synchronous or Trigger mode; setting the bit selects
Trigger mode operation. In both modes, the SYNCSEL
bits determine the sync/trigger source.
When the SYNCSEL bits are set to ‘00000’ and
ICTRIG is set, the module operates in Software Trigger
mode. In this case, capture operations are started by
manually setting the TRIGSTAT bit (ICxCON2<6>).
FIGURE 12-1:
INPUT CAPTURE BLOCK DIAGRAM
ICM2:ICM0
ICI1:ICI0
ICx Pin⁽¹⁾
Prescaler
Counter
1:1/4/16
ICTSEL2:ICTSEL0
Edge Detect Logic
and
Clock Synchronizer
Event and
Interrupt
Logic
Set ICxIF
Clock
Increment
16
IC Clock
Select
ICxTMR
4-Level FIFO Buffer
Sources
16
Trigger and
Sync Sources
Trigger and
Sync Logic _Reset
16
ICxBUF
SYNCSEL4:SYNCSEL0
TRIGGER
ICOV, ICBNE
System Bus
Note 1: The ICx inputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin
Select” for more information.
© 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 155