PIC24FJ256GB106-I Datasheet, PDF (177/328 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB110 FAMILY
REGISTER 14-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2
bit 1-0
SPRE2:SPRE0: Secondary Prescale bits (Master mode)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
...
000 = Secondary prescale 8:1
PPRE1:PPRE0: Primary Prescale bits (Master mode)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
Note 1:
2:
3:
4:
If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin
Select” for more information.
If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin
Select” for more information.
The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
If SSEN = 1, SSx must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select”
for more information.
REGISTER 14-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
FRMEN
SPIFSD SPIFPOL
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
SPIFE
SPIBEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support enabled
0 = Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control on SSx pin bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
Unimplemented: Read as ‘0’
SPIFE: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
SPIBEN: Enhanced Buffer Enable bit
1 = Enhanced Buffer enabled
0 = Enhanced Buffer disabled (Legacy mode)
© 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 175