PIC24FJ256GB106-I Datasheet, PDF (227/328 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB110 FAMILY
18.0 PARALLEL MASTER PORT
(PMP)
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
”Section 13. Parallel Master Port
(PMP)” (DS39713).
The Parallel Master Port (PMP) module is a parallel
8-bit I/O module, specifically designed to communicate
with a wide variety of parallel devices, such as commu-
nication peripherals, LCDs, external memory devices
and microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP is highly
configurable.
Key features of the PMP module include:
• Up to 16 Programmable Address Lines
• Up to 2 Chip Select Lines
• Programmable Strobe Options:
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support:
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer
• Programmable Wait States
• Selectable Input Voltage Levels
FIGURE 18-1:
PMP MODULE OVERVIEW
PIC24F
Parallel Master Port
PMA<0>
PMALL
PMA<1>
PMALH
PMA<13:2>
PMA<14>
PMCS1
PMA<15>
PMCS2
PMBE
PMRD
PMRD/PMWR
PMWR
PMENB
PMD<7:0>
PMA<7:0>
PMA<15:8>
Address Bus
Data Bus
Control Lines
Up to 16-Bit Address
EEPROM
Microcontroller
LCD
FIFO
Buffer
8-Bit Data
© 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 225