PIC24FJ256GA106T-I Datasheet, PDF (238/292 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit General Purpose Flash Microcontrollers with Peripheral Pin Select

PIC24FJ256GA110 FAMILY
REGISTER 24-2: CW2: FLASH CONFIGURATION WORD 2
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
R/PO-1
U-1
U-1
U-1
IESO
—
—
—
bit 15
r-0
R/PO-1
R/PO-1
R/PO-1
r
FNOSC2 FNOSC1 FNOSC0
bit 8
R/PO-1
FCKSM1
bit 7
R/PO-1
FCKSM0
R/PO-1
OSCIOFCN
R/PO-1
IOL1WAY
U-1
R/PO-1
R/PO-1
R/PO-1
—
I2C2SEL⁽¹⁾ POSCMD1 POSCMD0
bit 0
Legend:
R = Readable bit
PO = Program-once bit
-n = Value when device is unprogrammed
r = Reserved bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-16
bit 15
bit 14-12
bit 11
bit 10-8
bit 7-6
bit 5
bit 4
bit 3
bit 2
Unimplemented: Read as ‘1’
IESO: Internal External Switchover bit
1 = IESO mode (Two-Speed Start-up) enabled
0 = IESO mode (Two-Speed Start-up) disabled
Unimplemented: Read as ‘1’
Reserved: Always maintain as ‘0’
FNOSC2:FNOSC0: Initial Oscillator Select bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
FCKSM1:FCKSM0: Clock Switching and Fail-Safe Clock Monitor Configuration bits
1x = Clock switching and Fail-Safe Clock Monitor are disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
OSCIOFCN: OSCO Pin Configuration bit
If POSCMD1:POSCMD0 = 11 or 00:
1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2)
0 = OSCO/CLKO/RC15 functions as port I/O (RC15)
If POSCMD1:POSCMD0 = 10 or 01:
OSCIOFCN has no effect on OSCO/CLKO/RC15.
IOL1WAY: IOLOCK One-Way Set Enable bit
1 = The IOLOCK bit (OSCCON<6>)can be set once, provided the unlock sequence has been
completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.
0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been
completed
Unimplemented: Read as ‘1’
I2C2SEL: I2C2 Pin Select bit⁽¹⁾
1 = Use SCL2/SDA2 pins for I2C2
0 = Use ASCL2/ASDA2 pins for I2C2
Note 1: Implemented in 100-pin devices only; otherwise unimplemented, read as ‘1’.
DS39905B-page 236
Preliminary
© 2008 Microchip Technology Inc.