PIC24FJ256GA106T-I Datasheet, PDF (18/292 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit General Purpose Flash Microcontrollers with Peripheral Pin Select

PIC24FJ256GA110 FAMILY
TABLE 1-4: PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
64-Pin
TQFP
Pin Number
80-Pin
TQFP
100-Pin
TQFP
I/O
Input
Buffer
Description
CTED1
28
CTED2
27
CTPLS
29
CVREF
23
ENVREG
57
INT0
35
MCLR
7
OSCI
39
OSCO
40
PGEC1
15
PGED1
16
PGEC2
17
PGED2
18
PGEC3
11
PGED3
12
PMA0
30
PMA1
29
PMA2
8
PMA3
6
PMA4
5
PMA5
4
PMA6
16
PMA7
22
PMA8
32
PMA9
31
PMA10
28
PMA11
27
PMA12
24
PMA13
23
PMCS1
45
PMCS2
44
PMBE
51
PMD0
60
PMD1
61
PMD2
62
PMD3
63
PMD4
64
PMD5
1
PMD6
2
34
42
I
ANA CTMU External Edge Input 1.
33
41
I
ANA CTMU External Edge Input 2.
35
43
O
— CTMU Pulse Output.
29
34
O
— Comparator Voltage Reference Output.
71
86
I
ST Voltage Regulator Enable.
45
55
I
ST External Interrupt Input.
9
13
I
ST Master Clear (device Reset) Input. This line is brought low
to cause a Reset.
49
63
I
ANA Main Oscillator Input Connection.
50
64
O
ANA Main Oscillator Output Connection.
19
24
I/O
ST In-Circuit Debugger/Emulator/ICSP™ Programming Clock.
20
25
I/O
ST In-Circuit Debugger/Emulator/ICSP Programming Data.
21
26
I/O
ST In-Circuit Debugger/Emulator/ICSP Programming Clock.
22
27
I/O
ST In-Circuit Debugger/Emulator/ICSP Programming Data.
15
20
I/O
ST In-Circuit Debugger/Emulator/ICSP Programming Clock.
16
21
I/O
ST In-Circuit Debugger/Emulator/ICSP Programming Data.
36
44
I/O
ST Parallel Master Port Address Bit 0 Input (Buffered Slave
modes) and Output (Master modes).
35
43
I/O
ST Parallel Master Port Address Bit 1 Input (Buffered Slave
modes) and Output (Master modes).
10
14
O
— Parallel Master Port Address (Demultiplexed Master
8
12
O
— ^modes).
7
11
O
—
6
10
O
—
24
29
O
—
23
28
O
—
40
50
O
—
39
49
O
—
34
42
O
—
33
41
O
—
30
35
O
—
29
34
O
—
57
71
I/O ST/TTL Parallel Master Port Chip Select 1 Strobe/Address Bit 15.
56
70
O
ST Parallel Master Port Chip Select 2 Strobe/Address Bit 14.
63
78
O
— Parallel Master Port Byte Enable Strobe.
76
93
I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or
77
94
I/O ST/TTL ^{Address/Data (Multiplexed Master modes).}
78
98
I/O ST/TTL
79
99
I/O ST/TTL
80
100
I/O ST/TTL
1
3
I/O ST/TTL
2
4
I/O ST/TTL
PMD7
PMRD
PMWR
Legend:
3
3
5
53
67
82
52
66
81
TTL = TTL input buffer
ANA = Analog level input/output
I/O ST/TTL
O
— Parallel Master Port Read Strobe.
O
— Parallel Master Port Write Strobe.
ST = Schmitt Trigger input buffer
I²C™ = I²C/SMBus input buffer
DS39905B-page 16
Preliminary
© 2008 Microchip Technology Inc.